No abstract available.
Minimally buffered deflection routing with in-order delivery in a torus
Bufferless deflection routing is a serious alternative to wormhole flow control and packet switching. It is based on the principle of deflecting a flit to a non-optimal route instead of buffering it, when two flits compete for the same link. The major ...
Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect
Most Network-on-Chip routers dedicate a set of buffers to the input and/or output ports. This design decision leads to buffer underutilization especially when running applications with non-uniform traffic patterns. In order to maximize resource usage ...
A Novel Approach to Reduce Packet Latency Increase Caused by Power Gating in Network-on-Chip
The power gating technique is an effective way to reduce the high static power consumption in a Network-on-Chip (NoC). However, with notable wakeup delay, the power gating technique incurs significant packet latency increase. In this paper, we propose a ...
Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling
Photonic network-on-chip (PNoC) architectures employ photonic waveguides with dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for on-off-keying (OOK) based signal modulation, to enable high bandwidth on-...
Energy and Area Efficient Near Field Inductive Coupling: A Case Study on 3D NoC
Near Field Inductive Coupling (NFIC) enables design of energy efficient and robust three-dimensional (3D) manycore systems. The associated design challenges and the trade-offs of the NFIC-based vertical links depend on achievable data-rates, energy and ...
Achieving Lightweight Multicast in Asynchronous NoCs Using a Continuous-Time Multi-Way Read Buffer
Multicast communication (1-to-many) is common in parallel architectures and emerging areas such as neuromorphic computing. However, there is very limited research in supporting multicast in asynchronous NoCs. This paper proposes a new parallel multicast ...
BiNoCHS: Bimodal Network-on-Chip for CPU-GPU Heterogeneous Systems
CPU-GPU heterogeneous systems are emerging as architectures of choice for high-performance energy-efficient computing. Designing on-chip interconnects for such systems is challenging; CPUs typically benefit greatly from optimizations that reduce latency,...
Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable
In this paper, we present a novel synchoros VLSI design scheme that discretizes space uniformly. Synchoros derives from the Greek word chóros for space. We propose raising the physical design abstraction to register transfer level by using coarse grain ...
System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip
The network-on-Chip (NoC) is a critical subsystem for many large-scale systems-on-chip (SoC). We present a complete framework for the design and optimization of NoCs at the system-level. By combining a library of pre-designed configurable NoC modules ...
Addressing Extensibility and Fault Tolerance in CAN-based Automotive Systems
The design of automotive electronic systems needs to address a variety of important objectives, including safety, performance, fault tolerance, reliability, security, extensibility, etc. To obtain a feasible design, timing constraints must be satisfied ...
JAMS: Jitter-Aware Message Scheduling for FlexRay Automotive Networks
FlexRay is becoming a popular in-vehicle communication protocol for the next generation x-by-wire applications such as drive-by-wire and steer-by-wire. The protocol supports both time-triggered and event-triggered transmissions. One of the important ...
Hybrid Automotive In-Vehicle Networks
The design of automotive in-vehicle networks is influenced by several factors like bandwidth, real-time properties, reliability and cost. This has led to a number of protocols and communication standards like CAN, MOST, FlexRay and more recently the use ...
Fairness-Oriented and Location-Aware NUCA for Many-Core SoC
Non-uniform cache architecture (NUCA) is often employed to organize the last level cache (LLC) by Networks-on-Chip (NoC). However, along with the scaling up for network size of Systems-on-Chip (SoC), two trends gradually begin to emerge. First, the ...
On the Accuracy of Stochastic Delay Bound for Network on Chip
Delay bound guarantee in network on chip (NoC) is important for hard real-time applications, and deterministic network calculus (DNC) is a effective tool for delay bound modeling. But for soft real-time applications, delay bound derivation using DNC is ...
SMART: A Scalable Mapping And Routing Technique for Power-Gating in NoC Routers
Reducing the size of the technology increases leakage power in Network-on-Chip (NoC) routers drastically. Power-gating, particularly in NoC routers, is one of the most efficient approaches for alleviating the leakage power. Although applying power-...
On Runtime Communication- and Thermal-aware Application Mapping in 3D NoC
Many-core systems connected by 3D Network-on-Chips (NoC) are emerging as a promising computation engine for systems like cloud computing servers, big data systems, etc. Mapping applications at runtime to 3D NoCs is the key to maintain high throughput of ...
XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs
In this paper, we propose a method to design low latency and low energy networks for 3D Network-on-Chip (3D-NoC). Recent many-core processors require low-latency interconnection networks since the increasing number of cores limits the network ...
3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs
- Biresh Kumar Joardar,
- Wonje Choi,
- Ryan Gary Kim,
- Janardhan Rao Doppa,
- Partha Pratim Pande,
- Diana Marculescu,
- Radu Marculescu
As deep learning technology is increasingly employed in diverse applications domains, the demand for computational power to enable these algorithms also increases. In this respect, high-performance three-dimensional (3D) heterogeneous manycore systems ...
Rethinking NoCs for Spatial Neural Network Accelerators
Applications across image processing, speech recognition, and classification heavily rely on neural network-based algorithms that have demonstrated highly promising results in accuracy. However, such algorithms involve massive computations that are not ...
Adaptive Manycore Architectures for Big Data Computing
This work presents a cross-layer design of an adaptive manycore architecture to address the computational needs of emerging big data applications within the technological constraints of power and reliability. From the circuits end, we present links with ...
Recommendations
Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
NOCS '17 | 44 | 14 | 32% |
Overall | 44 | 14 | 32% |