Abstract
There has been a surge of interest in Non-Volatile Memory (NVM) in recent years. With many advantages, such as density and power consumption, NVM is carving out a place in the memory hierarchy and may eventually change our view of computer architecture. Many NVMs have emerged, such as Magnetoresistive random access memory (MRAM), Phase Change random access memory (PCM), Resistive random access memory (ReRAM), and Ferroelectric random access memory (FeRAM), each with its own peculiar properties and specific challenges. The scientific community has carried out a substantial amount of work on integrating those technologies in the memory hierarchy. As many companies are announcing the imminent mass production of NVMs, we think that it is time to have a step back and discuss the body of literature related to NVM integration. This article surveys state-of-the-art work on integrating NVM into the memory hierarchy. Specially, we introduce the four types of NVM, namely, MRAM, PCM, ReRAM, and FeRAM, and investigate different ways of integrating them into the memory hierarchy from the horizontal or vertical perspectives. Here, horizontal integration means that the new memory is placed at the same level as an existing one, while vertical integration means that the new memory is interleaved between two existing levels. In addition, we describe challenges and opportunities with each NVM technique.
- J. Ahn and K. Choi. 2012. Lower-bits cache for low power STT-RAM caches. In Proceedings of ISCAS, 480--483. Google ScholarCross Ref
- A. Akel, A. M. Caulfield, T. I. Mollov, R. K. Gupta, and S. Swanson. 2011. Onyx: A protoype phase change memory storage array. In Proceedings of HotStorage.Google Scholar
- H. Akinaga and H. Shima. 2010. Resistive random access memory (ReRAM) based on metal oxides. Proc. IEEE 98, 2 (2010), 2237--2251. Google ScholarCross Ref
- A. Athmanathan, M. Stanisavljevic, N. Papandreou, H. Pozidis, and E. Eleftheriou. 2016. Multilevel-cell phase-change memory: a viable technology. IEEE J. Emerg. Select. Top. Circ. Syst. 6, 1 (2016), 87--100. Google ScholarCross Ref
- A. Awad, S. Blagodurov, and Y. Solihin. 2016. Write-aware management of NVM-based memory extensions. In Proceedings of ICS. Article 9.Google Scholar
- S. Baek, J. Choi, D. Lee, and S. H. Noh. 2013. Energy-efficient and high-performance software architecture for storage class memory. ACM Trans. Embed. Comput. Syst. 12, 3 (2013). Article 81. Google ScholarDigital Library
- R. Bishnoi, F. Oboril, M. Ebrahimi, and M. B. Tahoori. 2014. Avoiding unnecessary write operations in STT-MRAM for low power implementation. In Proceedings of ISQED. 548--553. Google ScholarCross Ref
- M. Bjørling, P. Bonnet, L. Bouganim, and N. Dayan. 2013. The necessary death of the block device interface. In Proceedings of CIDR.Google Scholar
- S. Bock, S. B. Childers, R. Melhem, D. Mosse, and Y. Zhang. 2011. Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory. In Proceedings of ISPASS. 56--65. Google ScholarDigital Library
- J. Boukhobza. 2013. Flashing in the cloud: shedding some light on NAND flash memory storage systems. 2013. Data Intensive Storage Services for Cloud Environments. IGI Global, 241--266.Google Scholar
- J. Boukhobza and P. Olivier. 2017. Flash memory integration, Elsevier.Google Scholar
- G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy. 2008. Overview of candidate device technologies for storage-class memory. IBM J. Res. Dev. 52, 4 (2008), 449--464. Google ScholarDigital Library
- J. Carter and K. Rajamani. 2010. Designing energy efficient servers and data centers. Computer 43, 7 (2010), 76--78. Google ScholarDigital Library
- A. M. Caulfield, J. 0 Coburn, T. Mollov, A. De, A. Akel, J. He, A. Jagatheesan, R. K. Gupta, A. Snavely, and S. Swanson. 2010. Understanding the impact of emerging non-volatile memories on high-performance, io-intensive computing. In Proceedings of SC, 1--11. Google ScholarDigital Library
- J. Chen, R. C. Chiang, H. H. Huang, and G. Venkataramani. 2012. Energy-aware writes to non-volatile main memory. ACM SIGOPS Operat. Syst. Rev. 45, 3 (2012), 48--52. Google ScholarDigital Library
- Y. Chen, H. Li, W. Zhang, and R. E. Pino. 2011a. 3D-HIM: A 3D high-density interleaved memory for bipolar RRAM design. In Proceedings of NANOARCH. 59--64, 2011. Google ScholarDigital Library
- Y. Chen, H. Li, Y. Chen, and R. E. Pino. 2011b. 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers. In Proceedings of DATE. 1--4.Google Scholar
- Y. Chen, W. Wong, H. Li, C. Koh, Y. Zhang, and W. Wen. 2013. On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM J. Emerg. Technol. Comput. Syst. 9, 2 (2013). Google ScholarDigital Library
- R. Chen, Z. Shao, and T. Li. 2016. Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach. In Proceedings of MICRO. 1--12. Google ScholarCross Ref
- H. Y. Cheng et al. 2016. LAP: Loop-block aware inclusion properties for energy-efficient asymmetric last level caches. In Proceedings of ISCA. 103--114. Google ScholarDigital Library
- W. C. Chien. 2010. Unipolar switching behaviors of RTO WOX RRAM. IEEE Electron. Device Lett. 31, 2 (2010), 126--128. Google ScholarCross Ref
- B. J. Choi et al. 2005. Resistive switching mechanism of TiO2 thin films grown by atomic-layer deposition. J. Appl. Phys. 98, 033715 (2005). Google ScholarCross Ref
- L. Chua. 1971. Memristor—the missing element. IEEE Trans. Circuit Theory. 18, 5 (1971), 507--519. Google ScholarCross Ref
- F. Clermidy, N. Jovanovic, S. Onkaraiah, H. Oucheikh, O. Thomas, O. Turkyilmaz, E. Vianello, J. Portal, and M. Bocquet. 2014. Resistive memories: Which applications? In Proceedings of DATE.Google Scholar
- G. Dhiman, R. Ayoub, and T. Rosing. 2009. PDRAM: A hybrid PRAM and DRAM main memory system. In Proceedings of DAC. 664--469. Google ScholarDigital Library
- I. H. Doh, J. Choi, D. Lee, and S. H. Noh. 2007. Exploiting non-volatile RAM to enhance flash file system performance. In Proceedings of EMSOFT. 164--173. Google ScholarDigital Library
- W. Dong et al. 2015. Minimizing update bits of NVM-based main memory using bit flipping and cyclic shifting. In Proceedings of HPCC/CSS/ICESS. 290--295.Google ScholarDigital Library
- X. Dong, C. Xu, Y. Xie, and N. P. Jouppi. 2012. NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 31, 7 (2012), 994--1007. Google ScholarDigital Library
- X. Dong, N. P. Jouppi, and Y. Xie. 2013. A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies. In Proceedings of ISPASS. 140--141. Google ScholarCross Ref
- Y. Du, M. Zhou, B. R. Childers, D. Mossé, and R. Melhem. 2013. Bitmapping for balanced PCM cell programming. In Proceedings of ISCA. 428--439.Google Scholar
- S. R. Dulloor, A. Roy, Z. Zhao, N. Sundaram, N. Satish, R. Sankaran, J. Jackson, and K. Schwan. 2016. Data tiering in heterogeneous memory systems. In Proceedings of EuroSys. Article 15. Google ScholarDigital Library
- K. Eshraghian et al. 2011. Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines. IEEE Trans. on VLSI Systems. 19, 8 (2011), 1407--1417. Google ScholarDigital Library
- Everspin Technologies Inc. 2015. Retrieved November 2016 from https://www.everspin.com/64mb-spin-torque-mram-ddr3-dram-compatible.Google Scholar
- H. Fujii, K. Miyaji, K. Johguchi, K. Higuchi, C. Sun, and K. Takeuchi. 2012. x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression. In Proceedings of VLSIC. 134--135. Google ScholarCross Ref
- M. Fujimoto, H. Koyama, Y. Hosoi, K. Ishihara, and S. Kobayashi. 2006. High-speed resistive switching of TiO2/TiN nano-crystalline thin film, japan. J. Appl. Phys. 45, 8/11 (2006), L310--L312. Google ScholarCross Ref
- Y. Fujisaki. 2013. Review of emerging new solid-state non-volatile memories. Japan. J. Appl. Phys. 52 (2013). Google ScholarCross Ref
- S. Gao, B. He, and J. Xu. 2015. Real-time in-memory checkpointing for future hybrid memory systems. In Proceedings of ICS. 263--272. Google ScholarDigital Library
- J. F. Gibbons and W. E. Beadle. 1964. Switching properties of thin NiO films. Solid State Elect. 7, 11 (1964), 785--790. Google ScholarCross Ref
- N. Goswami, C. Bingyi, and L. Tao. 2013. Power-performance co-optimization of throughput core architecture using resistive memory. In Proceedings of HPCA. 342--353. Google ScholarDigital Library
- X. Guo, E. Ipek, and T. Soyata. 2010. Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. In Proceedings of ISCA. 371--382. Google ScholarDigital Library
- S. Gurumurthi. 2009. Architecting storage for the cloud computing area. IEEE Micro. 29, 6 (2009), 68--71. Google ScholarDigital Library
- A. Hassan, H. Vandierendonck, and D. S. Nikolopoulos. 2015. Energy-efficient in-memory data stores on hybrid memory hierarchies. In Proceedings of DaMoN. Google ScholarDigital Library
- Y. Hosoi et al. 2006. High speed unipolar switching resistance RAM (RRAM) technology. Proceedings of IEDM. 30.7.1--30.7.4. Google ScholarCross Ref
- Y. Huai. 2008. Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects. AAPPS Bulletin. 18, 6 (2008), 33--40.Google Scholar
- H. F. Huang and T. Jiang. 2014. Design and implementation of flash based NVDIMM. In Proceedings of NVMSA. 1--6. Google ScholarCross Ref
- A. Jadidi, M. Arjomand, and H. Sarbazi-Azad. 2011. High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement. In Proceedings of ISLPED. 79--84. Google ScholarCross Ref
- L. Jiang, Y. Zhang, and J. Yang. 2012. Elastic RESET for low power and long endurance MLC based phase change memory. In Proceedings of ISPLED. 39--44.Google Scholar
- L. Jiang, Y. Zhang, and J. Yang. 2014. Mitigating write disturbance in super-dense phase change memories. In Proceedings of DSN. 216--227. Google ScholarDigital Library
- L. Jiang, B. Zhao, J. Yang, and Y. Zhang. 2014. A low power and reliable charge pump design for phase change memories. In Proceedings of ISCA. 397--408. Google ScholarCross Ref
- Y. Jin, M. Shihab, and M. Jung. 2014. Area, power and latency considerations of STT-MRAM to substitute for main memory. In Proceedings of The Memory Forum.Google Scholar
- A. Jog, A. K. Mishra, X. Cong, X. Yuan, V. Narayanan, R. Iyer, and C. R. Das. 2012. Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs. In Proceedings of DAC. 243--252. Google ScholarDigital Library
- M. R. Jokar, M. Arjomand, and H. Sarbazi-Azad. 2016. Sequoia: A high-endurance NVM-based cache architecture. IEEE Transactions on VLSI Systems. 24, 3 (2016), 954--967. Google ScholarDigital Library
- Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, and Y. Xie. 2010. Energy-and endurance-aware design of phase change memory caches. In Proceedings of DATE. 136--141.Google Scholar
- J. Jung, Y. Won, E. Kim, H. Shin, and B. Jeon. 2010. FRASH: Exploiting storage class memory in hybrid file system for hierarchical storage. ACM Trans. On Storage 6, 1 (2010), Article 3. Google ScholarDigital Library
- J. Jung, Y. Nakata, M. Yoshimoto, and H. Kawaguchi. 2013. Energy-efficient spin-transfer torque RAM cache exploiting additional all-zero-data flags. In Proceedings of ISQED. 216--222.Google Scholar
- M. Jung, J. Shalf, and M. Kandemir. 2013. Design of a large-scale storage-class RRAM system. In Proceedings of ICS. 103--114. Google ScholarDigital Library
- H. Kanaya et al. 2004. A 0.602 μm2 nestled chain cell structure formed by one mask etching process for 64 Mbit FeRAM. In Proceedings of VLSl Technology. 150--151.Google Scholar
- D. Kang, S. Baek, J. Choi, D. Lee, S. H. Noh, and O. Mutlu. 2015. Amnesic cache management for non-volatile memory. In Proceedings of MSST. 1--13. Google ScholarCross Ref
- S. Kannan, A. Gavrilovska, and K. Schwan. 2016. pVM: Persistent virtual memory for efficient capacity scaling and object storage. In Proceedings of EuroSys. Article 13.Google Scholar
- Y. Kato, T. Yamada, and Y. Shimada. 2005. 0.18-lm nondestructive readout FeRAM using charge compensation technique. IEEE Trans. Elect. Dev. 52, 12 (2005), 2616--2621. Google ScholarCross Ref
- K. Kim and S. J. Ahn. 2005. Reliability investigations for manufacturable high density PRAM, Reliability. In Proceedings of IRPS. 157--162. Google ScholarCross Ref
- K. Kim. 2008. Future memory technology: challenges and opportunities. In Proceedings of VLSI-TSA, 5--9. Google ScholarCross Ref
- H. Kim, S. Seshadri, C. L. Dickey, and L. Chiu. 2014. Evaluating phase change memory for enterprise storage systems: A study of caching and tiering approaches. ACM Trans. Storage 10, 4 (2014), Article 15. Google ScholarDigital Library
- Y. Kim et al. 2011. Bi-layered RRAM with unlimited endurance and extremely uniform switching. In Proceedings of VLSIT, 52--53.Google Scholar
- P. Kogge et al. 2008. Exascale computing study: technology challenges in achieving exascale systems. DARPA Information Processing Techniques Office.Google Scholar
- M. P. Komalan et al. 2013. Design exploration of a NVM based hybrid instruction memory organization for embedded platforms. Design Auto. Embed. Syst. 17, 3--4 (2013), 459--483.Google Scholar
- M. Komalan, J. I. Gómez Pérez, C. Tenllado, P. Raghavan, M. Hartmann, and F. Catthoor. 2014. Feasibility exploration of NVM based I-cache through MSHR enhancements. In Proceedings of DATE, Article 21.Google Scholar
- M. H. Kryder and C. S. Kim. 2009. After hard drives—what comes next? IEEE Trans. Magnet. 45, 10 (2009), 3406--3413. Google ScholarCross Ref
- E. Kultursay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu. 2013. Evaluating stt-ram as an energy-efficient main memory alternative. In Proceedings of ISPASS. 256--267. Google ScholarCross Ref
- K. Kwon, S. H. Choday, Y. Kim, and K. Roy. 2014. AWARE (asymmetric write architecture with redundant blocks): a high write speed STT-MRAM cache architecture. IEEE Trans. on VLSI Systems. 22, 4 (2014), 712--720. Google ScholarDigital Library
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. 2009. Architecting phase change memory as a scalable dram alternative. In Proceedings of ISCA. 2--13. Google ScholarDigital Library
- H. Y. Lee et al. 2010. Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance. In Proceedings of IEDM. 19.7.1--19.7.4.Google Scholar
- D. Lee et al. 2006. Excellent uniformity and reproducible resistance switching characteristics of doped binary metal oxides for non-volatile resistance memory applications. In Proceedings of IEDM. 30.8.1--30.8.4. Google ScholarCross Ref
- E. Lee, H. Bahn, S. Yoo, and S. H. Noh. 2014. Empirical study of NVM storage: An operating system's perspective and implications. In Proceedings of MASCOTS. 405--410. Google ScholarDigital Library
- S. Lee, H. Bahn, and S. H. Noh. 2014. CLOCK-DWF: A write-history-aware page replacement algorithm for hybrid PCM and DRAM memory architectures. IEEE Trans. Comput. 63, 9 (2014), 2187--2200. Google ScholarDigital Library
- D. Li, J. S. Vetter, G. Marin, C. McCurdy, C. Cira, Z. Liu, and W. Yu. 2012. Identifying opportunities for byte-addressable non-volatile memory in extreme-scale scientific applications. In Proceedings of IPDPS. 945--956. Google ScholarDigital Library
- J. Li, C. Xue, and Y. Xu. 2011. STT-RAM based energy-efficiency hybrid cache for CMPs. In Proceedings of VLSI-SoC. 31--36. Google ScholarCross Ref
- X. Li, K. Lu, X. Wang, and X. Zhou. 2012. NV-process: A fault-tolerance process model based on non-volatile memory. In Proceedings of APSys. Article 1.Google Scholar
- Y. Li, Y. Chen, and A. Jones. 2012. A software approach for combating asymmetries of non-volatile memories. In Proceedings of ISLPED. 191--196. Google ScholarDigital Library
- Q. Li, J. Li, L. Shi, M. Zhao, J. C. Xue, and Y. He. 2014. Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems. IEEE Trans. VLSI Syst. 22, 8 (2014), 1829--1840. Google ScholarCross Ref
- Y. Liu, C. Zhou, X. Cheng, Hybrid SSD with PCM. 2011. In Proceedings of NVMTS. 1--5. Google ScholarCross Ref
- J. S. Meena, S. M. Sze, U. Chand, and T. Tseng. 2014. Overview of emerging non-volatile memory technologies. Nanoscale Res. Lett. 9, 526, (2014), 1--33.Google ScholarCross Ref
- F. Miao et al. 2011. Anatomy of a nanoscale conduction channel reveals the mechanism of a high-performance memristor. Adv. Mater. 23 (2011) 5633--5640. Google ScholarCross Ref
- A. Mirhoseini, M. Potkonjak, and F. Koushanfar. 2012. Coding-based energy minimization for phase change memory. In Proceedings of DAC. 68--76. Google ScholarDigital Library
- S. Mittal. 2013. Using cache-coloring to mitigate inter-set write variation in non-volatile caches. Technical report, Iowa State University.Google Scholar
- S. Mittal and J. S. Vetter. 2015a. AYUSH: A technique for extending lifetime of SRAM-NVM hybrid caches. IEEE Comput. Architect. Lett. 14, 2 (2015), 115--118. Google ScholarDigital Library
- S. Mittal, J. S. Vetter, and D. Li. 2015b. A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches. IEEE Trans. Parallel Distrib. Syst. 26, 6 (2015), 1524--1537. Google ScholarDigital Library
- S. Mittal and J. S. Vetter. 2016. A survey of software techniques for using non-volatile memories for storage and main memory systems. IEEE Trans. Parallel Distrib. Syst. 27, 5 (2016), 1537--1550. Google ScholarDigital Library
- S. Mittal. 2016. A survey of techniques for architecting processor components using domain-wall memory. J. Emerg. Technol. Comput. Syst. 13, 2, (2016), Article 29.Google ScholarDigital Library
- J. C. Mogul, E. Argollo, M. Shah, and P. Faraboschi. 2009. Operating system support for NVM+DRAM hybrid main memory. In Proceedings of HotOS.Google Scholar
- O. Mutlu. 2015. Main memory scaling: challenges and solution directions. More than Moore Technologies for Next Generation Computer Design, Springer. 127--153.Google Scholar
- D. Niu, C. Xu, N. Muralimanohar, N. P. Jouppi, and Y. Xie. 2012. Design trade-offs for high density cross-point resistive memory. In Proceedings of ISLPED. 209--214. Google ScholarDigital Library
- F. Oboril, R. Bishnoi, M. Ebrahimi, and M. B. Tahoori. 2015. Evaluation of hybrid memory technologies using SOT-MRAM for on-chip cache hierarchy. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 34, 3 (2015), 367--380. Google ScholarDigital Library
- S. Oikawa. 2014. Independent kernel/process checkpointing on non-volatile main memory for quick kernel rejuvenation. In Proceedings of ARCS. 233--244. Google ScholarDigital Library
- X. Ouyang, D. Nellans, R. Wipfel, D. Flynn, and D. K. Panda. 2011. Beyond block I/O: Rethinking traditional storage primitives. In Proceedings of HPCA. 301--311. Google ScholarCross Ref
- J. Park, D. Shin, and H. G. Lee. 2015. Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface. In Proceedings of VLSI-SoC. 104--109. Google ScholarCross Ref
- S. Park, Y. Kim, B. Urgaonkar, J. Lee, and E. Seo. 2011. A comprehensive study on energy efficiency of flash memory storages. J. Syst. Architect. 57, 4 (2011), 354--365. Google ScholarDigital Library
- S. P. Park, S. Gupta, N. Mojumder, A. Raghunathan, and K. Roy. 2012. Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture. In Proceedings of DAC. 492--497. Google ScholarDigital Library
- Y. Park, S. K. Park, K. H. Park, Linux Kernel Support to Exploit Phase Change Memory. 2010. In Proceedings of the Linux Symposium. 217--224.Google Scholar
- M. K. Qureshi, V. Srinivasan, and J. A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. In Proceedings of ISCA. 24--33. Google ScholarDigital Library
- M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano. 2010. Improving read performance of phase change memories via write cancellation and write pausing. In Proceedings HPCA. Google ScholarCross Ref
- M. K. Qureshi, S. Gurumurthi, and B. Rajendran. 2011. Phase change memory: From devices to systems. Synthesis Lectures on Computer Architecture, Morgan 8 Claypool.Google Scholar
- P. Ranganathan. 2011. From microprocessors to nanostores: Rethinking data-centric systems. Computer 44, 1 (2011), 39--48. Google ScholarDigital Library
- M. Rasquinha, D. Choudhary, S. Chatterjee, S. Mukhopadhyay, and S. Yalamanchili. 2010. An energy efficient cache design using spin torque transfer (STT) RAM. In Proceedings of ISLPED. 389--394. Google ScholarDigital Library
- D. Roberts, T. Kgil, and T. Mudge. 2009. Integrating NAND flash devices onto servers. Commun. ACM 52, 4 (2009), 98--106. Google ScholarDigital Library
- U. Russo, D. Ielmini, A. Redaelli, and A. L. Lacaita. 2008. Modeling of programming and read performance in phase-change memories—Part I: Cell optimization and scaling. IEEE Trans. Electron Devices 55, 2 (2008), 506--514. Google ScholarCross Ref
- R. Salkhordeh and H. Asadi. 2016. An operating system level data migration scheme in hybrid DRAM-NVM memory architecture. In Proceedings of DATE. 936--941. Google ScholarCross Ref
- M. H. Samavatian, H. Abbasitabar, M. Arjomand, and H. Sarbazi-Azad. 2014. An efficient STT-RAM last level cache architecture for GPUs. In Proceedings DAC. 1--6.Google Scholar
- G. S. Sandhu. 2013. Emerging memories technology landscape. In Proceedings of NVMTS. 1--5. Google ScholarCross Ref
- S. Schechter, G. H. Loh, K. Straus, and D. Burger. 2010. Use ECP, not ECC, for hard failures in resistive memories, SIGARCH Comput. Architect. News 38, 3 (2010), 141--152. Google ScholarDigital Library
- S. Senni, L. Torres, G. Sassatelli, A. Bukto, and B. Mussard. 2014. Exploration of magnetic RAM based memory hierarchy for multicore architecture. In Proceedings of ISVLSI. 248--251. Google ScholarDigital Library
- S. Senni, L. Torres, G. Sassatelli, A. Gamatie, and B. Mussard. 2015. Emerging non-volatile memory technologies exploration flow for processor architecture. In Proceedings of ISVLSI. 460--460. Google ScholarCross Ref
- S. Sheu et al. 2011. A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. In Proceedings of ISSCC. 200--202. Google ScholarCross Ref
- H. Shiga et al. 2009. A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. In Proceedings of ISSCC. 464--465. Google ScholarCross Ref
- A. Shilov. 2016. Western digital to use 3D ReRAM as storage class memory (SCM) for special-purpose SSDs. ANANDTECH.Google Scholar
- C. W. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. R. Stan. 2011. Relaxing non-volatility for fast and energy-efficient STT-RAM caches. In Proceedings HPCA. 50--61. Google ScholarCross Ref
- SNIA. 2015. NVM Programming Model (NPM). Retrieved from http://www.snia.org/sites/default/files/technical_work/final/NVMProgrammingModel_v1.1.pdf.Google Scholar
- D B. Sturkov, G. S. Snider, and R. S. William. 2008. The missing memristor found. Nature 453 (2008), 80--83. Google ScholarCross Ref
- G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen. 2009. A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In Proceedings of HPCA. 239--249. Google ScholarCross Ref
- G. Sun, Y. Joo, Y. Chen, D. Niu, Y. Xie, Y. Chen, and H. Li. 2010. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. 2010. In Proceedings of HPCA. 1--12.Google Scholar
- G. Sun, D. Niu, J. Ouyang, and Y. Xie. 2011. A frequent-value based PRAM memory architecture. In Proceedings of ASP-DAC. 211--216. Google ScholarCross Ref
- H. Sun, K. Miyaji, K. Johguchi, and K. Takeuchi. 2014. A high performance and energy-efficient cold data eviction algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD. IEEE Trans. Circ. Syst. I, 61, 2 (2014), 382--392. Google ScholarCross Ref
- Z. Sun, X. Bi, H. Li, W. Wong, Z. Ong, X. Zhu, and W. Wu. 2011. Multi retention level STT-RAM cache designs with a dynamic refresh scheme. In Proceedings of MICRO. 329--338 Google ScholarDigital Library
- Z. Sun, Z. Jia, X. Cai, Z. Zhang, and L. Ju. 2015. AIMR: An adaptive page management policy for hybrid memory architecture with NVM and DRAM. In Proceedings of HPCC/CSS/ICESS. 284--289.Google Scholar
- A. Suresh, P. Cicotti, and L. Carrington. 2014. Evaluation of emerging memory technologies for HPC, data intensive applications. In Proceedings of CLUSTER. 239--247. Google ScholarCross Ref
- S. Syu, Y. Shao, and I. Lin. 2013. High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy. In Proceedings of GLSVLSI. 19--24. Google ScholarDigital Library
- S. Tanakamaru, M. Doi, and K. Takeuchi. 2014. NAND flash memory/ReRAM hybrid unified solid-state-storage architecture. IEEE Trans. Circ. Syst. I, 61, 4 (2014), 1119--1132. Google ScholarCross Ref
- G. Uh, Y. Wang, D. Whalley, S. Jinturkar, C. Burns, and V. Cao. 1999. Effective exploitation of a zero overhead loop buffer. In Proceedings of LCTES. 10--19. Google ScholarDigital Library
- H. Venkatesh and S. Singh. 2015. FRAMs fit wearable electronics like a glove, electronic design. Retrieved November 2016 from http://electronicdesign.com/ memory/frams-fit-wearable-electronics-glove.Google Scholar
- J. S. Vetter and S. Mittal. 2015. Opportunities for nonvolatile memory systems in extreme-scale high-performance computing. Comput. Sci. Eng. 17, 2 (2015), 73--82. Google ScholarDigital Library
- J. Wang, X. Dong, Y. Xie, and N. P. Jouppi. 2013. i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations. In Proceedings of HPCA. 234--245.Google Scholar
- J. Wang, X. Dong, Y. Xie, and N. P. Jouppi. 2014. Endurance-aware cache line management for non-volatile caches. ACM Trans. Archit. Code Optim. 11, 1 (2014a). Google ScholarDigital Library
- J. Wang, X. Dong, and Y. Xie. 2014. Building and optimizing MRAM-based commodity memories. ACM Trans. Archit. Code Optim. 11, 4 (2014b). Google ScholarDigital Library
- R. Wang, L. Jiang, Y. Zhang, L. Wang, and J. Yang. 2015a. Selective restore: An energy efficient read disturbance mitigation scheme for future STT-MRAM. In Proceedings of DAC. Article 21.Google Scholar
- R. Wang, L. Jiang, Y. Zhang, and J. Yang. 2015b. SD-PCM: Constructing reliable super dense phase change memory under write disturbance. In Proceedings of ASPLOS. 19--31. Google ScholarDigital Library
- R. Wang, L. Jiang, Y. Zhang, L. Wang, and J. Yang. 2015c. Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory. In Proceedings of DAC. Article 88. Google ScholarDigital Library
- Z. Wang, D. A. Jimenez, X. Cong, S. Guangyu, and Y. Xie. 2014. Adaptive placement and migration policy for an STT-RAM-based hybrid cache. In Proceedings of HPCA. 13--24. Google ScholarCross Ref
- Z. Wang, Z. Gu, M. Yao, and Z. Shao. 2015. Endurance-aware allocation of data variables on NVM-based scratchpad memory in real-time embedded systems. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 34, 10 (2015), 1600--1612. Google ScholarCross Ref
- Q. Wei, J. Chen, and C. Chen. 2015. Accelerating file system metadata access with byte-addressable nonvolatile memory. ACM Trans. Storage 11, 3 (2015), Article 12. Google ScholarDigital Library
- W. Wei, D. Jiang, S. A. McKee, J. Xiong, and M. Chen. 2015. Exploiting program semantics to place data in hybrid memory. In Proceedings of PACT. 163--173. Google ScholarDigital Library
- R. S. William. 2008. How we found the missing memristor. IEEE Spectrum. 45 (2008), 28--35. Google ScholarDigital Library
- R. Winter. 2008. Why are data warehouses growing so fast? Retrieved from http://www.b-eye-network.com/channels/1138/view/7188.Google Scholar
- W. Wong. 2016. FRAM delivers unified memory for 16-bit microcontroller. Electronic Design.Google Scholar
- J. Y. Wu et al. 2015. Greater than 2-bits/cell MLC storage for ultrahigh density phase change memory using a novel sensing scheme. In Proceedings of VLSI Technology. T94--T95.Google Scholar
- P. Wu, D. Li, Z. Chen, J. S. Vetter, and S. Mittal. 2016. Algorithm-directed data placement in explicitly managed non-volatile memory. In Proceedings of HPDC. 141--152. Google ScholarDigital Library
- X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie. 2009. Hybrid cache architecture with disparate memory technologies. In Proceedings of ISCA. 34--45. Google ScholarDigital Library
- F. Xia, D. Jiang, J. Xiong, and N. Sun. 2015. A survey of phase change memory systems. J. Comput. Sci. Technol. 30, 1 (2015), 121--144. Google ScholarCross Ref
- C. Xu, X. Dong, N. P. Jouppi, and Y. Xie. 2011. Design implications of memristor-based RRAM cross-point structures. In Proceedings of DATE.Google Scholar
- C. Xu, D. Niu, N. Muralimanohar, N. P. Jouppi, and Y. Xie. 2013. Understanding the trade-offs in multi-level cell ReRAM memory design. In Proceedings of DAC. Article 108. Google ScholarDigital Library
- C. Xu, D. Niu, N. Muralimanoha, R. Balasubramonian, T. Zhang, S. Yu, and Y. Xie. 2015. Overcoming the challenges of crossbar resistive memory architectures. In Proceedings of HPCA. 476--488. Google ScholarCross Ref
- C. Xu, D. Niu, Y. Zheng, S. Yu, and Y. Xie. 2014. Reliability-aware cross-point resistive memory design. In Proceedings of GLSVLSI. 145--150. Google ScholarDigital Library
- W. Xu, J. Liu, and T. Zhang. 2009. Data manipulation techniques to reduce phase change memory write energy. In Proceedings of ISPLED. 237--242. Google ScholarDigital Library
- C. J. Xue, Y. Zhang, Y. Chen, G. Sun, J. J. Yang, and H. Li. 2011. Emerging non-volatile memories: Opportunities and challenges. In Proceedings of CODES+ISSS. 325--334.Google Scholar
- B. D. Yang, J. E. Lee, J. S. Kim, J. Cho, S. Y. Lee, and B. G. Yu. 2007. A low power phase-change random access memory using a data-comparison write scheme. In Proceedings of ISCAS. 3014--3017. Google ScholarCross Ref
- J. J. Yang and R. S. Williams. 2013. Memristive devices in computing system: Promises and challenges. ACM J. Emerg. Technol. Comput. Syst. 9, 2 (2013), Article 11. Google ScholarDigital Library
- J. J. Yang, F. Miao, M. D. Pickett, D. A. A. Ohlberg, D. R. Stewart, C. N. Lau, and R. S. Williams. 2009. The mechanism of electroforming of metal oxide memristive switches. Nanotechnology 20 215201 (2009). Google ScholarCross Ref
- J. J. Yang et al. 2010. Diffusion of adhesion layer metals controls nanoscale memristive switching. Adv. Mater. 22, 36 (2010), 4034--4038. Google ScholarCross Ref
- S. H. Yang, and Y. S Ryu. 2013. A buffer management for STT-MRAM based hybrid main memory in sensor nodes. In Proceedings of ICCNCE. 286--289. Google ScholarCross Ref
- S. Yazdanshenas, M. R. Pirbasti, M. Fazeli, and A. Patooghy. 2014. Coding last level STT-RAM cache for high endurance and low power. Comput. Architect. Lett. 13, 2 (2014), 73--76. Google ScholarDigital Library
- J. H. Yoon, E. H. Nam, Y. J. Seong, H. Kim, B. S. Kim, S. L. Min, and Y. Cho. 2008. Chameleon: A high performance flash/FRAM hybrid solid state disk architecture. Comput. Architect. Lett. 7, 1 (2008), 17--20. Google ScholarDigital Library
- K. Yoongu, R. Daly, J. Kim, C. Fallin, L. Ji Hye, L. Donghyuk, C. Wilkerson, K. Lai, and O. Mutlu. 2014. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. In Proceedings of ISCA. 361--372.Google Scholar
- S. Yu, P. Y. Chen, Emerging Memory Technologies: Recent Trends and Prospects. 2016. IEEE Solid-State Circuits Mag. 8, 2 (2016), 43--56. Google ScholarCross Ref
- J. Yue, Y. Zhu. 2013a. Accelerating write by exploiting PCM asymmetries. In Proceedings of HPCA. 282--293.Google Scholar
- J. Yue and Y. Zhu. 2013b. Exploiting subarrays inside a bank to improve phase change memory performance. In Proceedings of DATE. 386--391. Google ScholarCross Ref
- J. Yun, S. Lee, and S. Yoo. 2012. Bloom filter-based dynamic wear leveling for phase-change RAM. In Proceedings of DATE. 1513--1518.Google Scholar
- Q. Zhang, L. Chang, and R. Boutaba. 2010. Cloud computing: State-of-the-art and research challenges. J. Int. Services Appl. 1, 1 (2010), 7--18. Google ScholarCross Ref
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. 2009a. A durable and energy efficient main memory using phase change memory technology. In Proceedings of ISCA. 14--23. Google ScholarDigital Library
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. 2009b. Energy reduction for STT-RAM using early write termination. In Proceedings of ICCAD. 264--268. Google ScholarDigital Library
Index Terms
- Emerging NVM: A Survey on Architectural Integration and Research Challenges
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