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Exploiting Chip Idleness for Minimizing Garbage Collection—Induced Chip Access Conflict on SSDs

Published: 05 October 2017 Publication History

Abstract

Solid state drives (SSDs) are normally constructed with a number of parallel-accessible flash chips, where host I/O requests are processed in parallel. In addition, there are many internal activities in SSDs, such as garbage collection and wear leveling induced read, write, and erase operations, to solve the issues of inability of in-place updates and limited lifetime. When internal activities are triggered on a chip, the chip will be blocked. Our preliminary studies on several workloads show that when internal activities are frequently triggered, the host I/O performance will be significantly impacted because of the access conflict between them. In this work, in order to improve the access conflict induced performance degradation, a novel access conflict minimization scheme is proposed. The basic idea of the scheme is motivated by an interesting observation in SSDs: several chips are idle when other chips are busy with internal activities and host I/O requests. Based on this observation, we propose to schedule internal activities induced operations for minimized access conflict by exploiting the idleness of the multiple chips of SSDs. This approach is realized by two steps: First, read internal activities accessed data to the controller; second, by exploiting the idle chips during internal activities, write internal activities accessed data back to these idle chips. With this scheme, the internal activities can be processed with minimized access conflict to the host requests. Simulation results show that the proposed approach significantly reduces the access conflict, and in turn leads to a significant performance improvement of SSDs.

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 23, Issue 2
March 2018
341 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/3149546
  • Editor:
  • Naehyuck Chang
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 05 October 2017
Accepted: 01 July 2009
Revised: 01 July 2009
Received: 01 January 2007
Published in TODAES Volume 23, Issue 2

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Author Tags

  1. Garbage collection
  2. SSD
  3. access conflicts
  4. chip idleness
  5. parallelism

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  • Research-article
  • Research
  • Refereed

Funding Sources

  • National 863 Programs
  • NSFC
  • Fundamental Research Funds for the Central Universities
  • Huawei Innovation Research Program (HIRP)
  • Fundamental Research Funds for Graduate Scientific Research and Innovation Foundation of Chongqing, China

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  • (2024)Page Type-Aware Full-Sequence Program Scheduling via Reinforcement Learning in High Density SSDsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344471843:11(3696-3707)Online publication date: Nov-2024
  • (2023)Re-aligning Across-page Requests for Flash-based Solid-state DrivesProceedings of the 52nd International Conference on Parallel Processing10.1145/3605573.3605652(736-745)Online publication date: 7-Aug-2023
  • (2023)ADAR: Application-Specific Data Allocation and Reprogramming Optimization for 3-D TLC Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321039042:6(1824-1837)Online publication date: 1-Jun-2023
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  • (2021)Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDsACM Transactions on Architecture and Code Optimization10.1145/346043318:4(1-25)Online publication date: 31-Dec-2021
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  • (2020)Boosting the Performance of SSDs via Fully Exploiting the Plane Level ParallelismIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2020.298789431:9(2185-2200)Online publication date: 1-Sep-2020
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