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Repair of FPGA-Based Real-Time Systems With Variable Slacks

Published: 15 January 2018 Publication History

Abstract

Field-programmable gate arrays (FPGAs) based on SRAM cells are an attractive alternative for real-time system designers, as they offer high density, low cost, and high performance. The use of SRAM cells in the FPGA’s configuration memory, while enabling these desirable characteristics, also creates a reliability hazard as RAM cells are susceptible to single-event upsets (SEUs). The usual approach is the use of double or triple redundancy allied with a correction mechanism, such as periodic scrubbing. Although scrubbing is an effective technique to remove SEU-induced errors, the repair of real-time systems presents specific challenges, such as avoiding failures by missing real-time deadlines. In this article, a novel approach is proposed to use a deadline-aware scrubbing scheme with negligible area costs that dynamically chooses the scrubbing starting position. Such a scheme allows us to avoid missing real-time deadlines while maximizing the repair probability given a bounded repair time. Our approach reduces the failure rate, considering the probability of missing deadlines due to faults, by 33.39% on average, with an average area cost of 1.23%.

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Cited By

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  • (2018)FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA DesignsIEEE Transactions on Aerospace and Electronic Systems10.1109/TAES.2018.282820154:6(2695-2712)Online publication date: Dec-2018

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 23, Issue 2
March 2018
341 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/3149546
  • Editor:
  • Naehyuck Chang
Issue’s Table of Contents
© 2018 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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Publication History

Published: 15 January 2018
Accepted: 01 September 2017
Revised: 01 February 2017
Received: 01 August 2016
Published in TODAES Volume 23, Issue 2

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Author Tags

  1. Field-programmable gate arrays (FPGAs)
  2. fault diagnosis
  3. fault tolerance
  4. real time
  5. scrubbing

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  • Research-article
  • Research
  • Refereed

Funding Sources

  • Conselho Nacional de Desenvolvimento Científco e Tecnológico (CNPq)
  • Instituto Federal de Educação, Ciência e Tecnologia do Rio Grande do Sul (IFRS)
  • Fundação de Amparo à Pesquisa do Estado do Rio Grande do Sul (FAPERGS)

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  • (2018)FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA DesignsIEEE Transactions on Aerospace and Electronic Systems10.1109/TAES.2018.282820154:6(2695-2712)Online publication date: Dec-2018

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