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Multi-Objective 3D Floorplanning with Integrated Voltage Assignment

Published: 27 November 2017 Publication History

Abstract

Voltage assignment is a well-known technique for circuit design, which has been applied successfully to reduce power consumption in classical 2D integrated circuits (ICs). Its usage in the context of 3D ICs has not been fully explored yet although reducing power in 3D designs is of crucial importance, for example, to tackle the ever-present challenge of thermal management. In this article, we investigate the effective and efficient partitioning of 3D designs into multiple voltage domains during the floorplanning step of physical design. In particular, we introduce, implement, and evaluate novel algorithms for effective integration of voltage assignment into the inner floorplanning loops. Our algorithms are compatible not only with the traditional objectives of 2D floorplanning but also with the additional objectives and constraints of 3D designs, including the planning of through-silicon vias (TSVs) and the thermal management of stacked dies. We test our 3D floorplanner extensively on the GSRC benchmarks as well as on an augmented version of the IBM-HB+ benchmarks. The 3D floorplans are shown to achieve effective trade-offs for power and delays throughout different configurations—our results surpass naïve low-power and high-performance voltage assignment by 17% and 10%, on average. Finally, we release our 3D floorplanning framework as open-source code.

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  • (2024)A Cost-Driven Chip Partitioning Method for Heterogeneous 3D IntegrationACM Transactions on Design Automation of Electronic Systems10.1145/367255829:4(1-27)Online publication date: 14-Jun-2024
  • (2024)Heat transfer enhancement for 3D chip thermal simulation and predictionApplied Thermal Engineering10.1016/j.applthermaleng.2023.121499236(121499)Online publication date: Jan-2024
  • (2023)ISP: An Improved Slicing Pair Code for Skewed Slicing Floorplan2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)10.1109/VLSID57277.2023.00051(205-210)Online publication date: Jan-2023
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 23, Issue 2
March 2018
341 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/3149546
  • Editor:
  • Naehyuck Chang
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 27 November 2017
Accepted: 01 September 2017
Revised: 01 September 2017
Received: 01 February 2007
Published in TODAES Volume 23, Issue 2

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Author Tags

  1. Voltage assignment
  2. power-performance optimization

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Cited By

View all
  • (2024)A Cost-Driven Chip Partitioning Method for Heterogeneous 3D IntegrationACM Transactions on Design Automation of Electronic Systems10.1145/367255829:4(1-27)Online publication date: 14-Jun-2024
  • (2024)Heat transfer enhancement for 3D chip thermal simulation and predictionApplied Thermal Engineering10.1016/j.applthermaleng.2023.121499236(121499)Online publication date: Jan-2024
  • (2023)ISP: An Improved Slicing Pair Code for Skewed Slicing Floorplan2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)10.1109/VLSID57277.2023.00051(205-210)Online publication date: Jan-2023
  • (2022)A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoCMicroelectronics Journal10.1016/j.mejo.2022.105536128(105536)Online publication date: Oct-2022
  • (2022)Chip PlanningVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-3-030-96415-3_3(53-93)Online publication date: 15-Jun-2022
  • (2019)A survey of optimization techniques for thermal-aware 3D processorsJournal of Systems Architecture10.1016/j.sysarc.2019.01.003Online publication date: Jan-2019
  • (2018)Optimization of Full-Chip Power Distribution Networks in 3D ICs2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICAM.2018.8596650(134-138)Online publication date: Nov-2018

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