skip to main content
research-article

iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis

Published: 11 June 2018 Publication History

Abstract

As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this article, we present compact and accurate timing macro modeling, which is the key to efficient and accurate hierarchical timing analysis. Our goal is to contain only a minimal amount of interface logic in our timing macro model. The main idea is to separate the interface logic into variant and constant timing regions. Then, the variant timing region is reserved for accuracy, while the constant timing region is reduced for compactness. For reducing the constant timing region, we propose anchor pin insertion and deletion by generalizing existing timing graph reduction techniques. Furthermore, we devise a lookup table index selection technique to achieve high model accuracy over the possible operating condition range. Compared with two common models used in industry, extracted timing model and interface logic model, our model has high model accuracy and small model size. Based on the TAU 2016 and 2017 timing macro modeling contest benchmark suites, our results show that our algorithm delivers superior efficiency and accuracy: Hierarchical timing analysis using our model can significantly reduce runtime and memory compared with flat timing analysis on the original design. Moreover, our algorithm outperforms TAU 2016 and 2017 contest winners in model accuracy, model size, model generation performance, and model usage performance.

References

[1]
Florentin Dartu and Qiuyang Wu. 2013. To do or not to do hierarchical timing? In Proceedings of the 2013 ACM International Symposium on Physical Design (ISPD'13). 180.
[2]
Babul Anunay. 2013. Hierarchical Timing Concepts. EDN Network. Retrieved from http://www.edn.com/design/integrated-circuit-design/4423327/Hierarchical-timing-concepts.
[3]
Sunil Walia. 2011. Reducing turnaround time with hierarchical timing analysis. EE Times. Retrieved from http://www.eetimes.com/document.asp?doc_id=1279120.
[4]
Chandu Visweswariah, Oleg Levitsky, Qiuyang Wu, Amit Shaligram, Alex Rubin, Guntram Wolski, Alexander Skourikhin, Larry Brown, and Igor Keller. 2013. EDA court: Hierarchical construction and timing sign-off of socs. In Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU’13). Retrieved from http://www.tauworkshop.com/2013/presentations/tau2013_hierarchy_panel.ppt.
[5]
Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, and Qiuyang Wu. 2002. Automated timing model generation. In Proceedings of the 39th annual ACM/IEEE Design Automation Conference (DAC'02). 146--151.
[6]
Liberty user guides and reference manual suite version 2013.03. 2013. Retrieved from https://www.synopsys.com.
[7]
Cho W. Moon, Harish Kriplani, and Krishna P. Belkhale. 2002. Timing model extraction of hierarchical blocks by graph reduction. In Proceedings of the 39th annual ACM/IEEE Design Automation Conference (DAC'02). 152--157.
[8]
Shuo Zhou, Yi Zhu, Yuanfang Hu, Roland Graham, Mike Hutton, and Chung-Kuan Cheng. 2006. Timing model reduction for hierarchical timing analysis. In Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design (ICCAD'06). 415--422.
[9]
Yu-Ming Yang, Yu-Wei Chang, and Iris Hui-Ru Jiang. 2014. iTimerC: Common path pessimism removal using effective reduction methods. In Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD'14). 600--605.
[10]
Jin Hu, Song Chen, Xin Zhao, and Xi Chen. 2016. TAU 2016 Timing contest on macro modeling. In Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'16). Retrieved from https://sites.google.com/site/taucontest2016/.
[11]
Song Chen, Akash Khandelwal, Xin Zhao, and Xi Chen. 2017. TAU 2017 Timing contest on macro modeling. In Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'17). Springer. Retrieved from https://sites.google.com/site/taucontest2017/.
[12]
J. Bhasker and Rakesh Chadha. 2009. Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer.
[13]
Tsung-Wei Huang, Pei-Ci Wu, and Martin D. F. Wong. 2014. Fast path-based timing analysis for CPPR. In Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD'14). 596--599.
[14]
Chandramouli V. Kashyap, Charles J. Alpert, Frank (Ying) Liu, and Anirudh Devgan. 2004. Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. (TCAD) 23, 4 (2004), 509--516.
[15]
Pei-Yu Lee, Iris Hui-Ru Jiang, Cheng-Ruei Li, Wei-Lun Chiu, and Yu-Ming Yang. 2015. iTimerC 2.0: Fast incremental timing and CPPR analysis. In Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD'15). 890--894.
[16]
Tsung-Wei Huang and Martin D. F. Wong. 2015. Opentimer: A high-performance timing analysis tool. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD'15). 895--902.
[17]
Pei-Yu Lee, Iris Hui-Ru Jiang, and Ting-You Yang. 2017. iTimerM: Compact and accurate timing macro modeling for efficient hierarchical timing analysis. In Proceedings of the 2017 ACM on International Symposium on Physical Design (ISPD'17). 83--89.

Cited By

View all
  • (2024)Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems PerspectiveIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.338335043:10(2840-2853)Online publication date: 1-Oct-2024
  • (2023)Accelerating Static Timing Analysis Using CPU–GPU Heterogeneous ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328626142:12(4973-4984)Online publication date: 1-Dec-2023
  • (2023)The Learnable Model-Based Genetic Algorithm for the IP Mapping ProblemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321502342:7(2350-2363)Online publication date: 1-Jul-2023
  • Show More Cited By

Index Terms

  1. iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 23, Issue 4
    Special Section on Advances in Physical Design Automation and Regular Papers
    July 2018
    316 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/3217208
    • Editor:
    • Naehyuck Chang
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Journal Family

    Publication History

    Published: 11 June 2018
    Accepted: 01 September 2017
    Revised: 01 August 2017
    Received: 01 May 2017
    Published in TODAES Volume 23, Issue 4

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. Hierarchical timing analysis
    2. extracted timing model
    3. interface logic model
    4. timing macro modeling

    Qualifiers

    • Research-article
    • Research
    • Refereed

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)28
    • Downloads (Last 6 weeks)3
    Reflects downloads up to 17 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems PerspectiveIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.338335043:10(2840-2853)Online publication date: 1-Oct-2024
    • (2023)Accelerating Static Timing Analysis Using CPU–GPU Heterogeneous ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328626142:12(4973-4984)Online publication date: 1-Dec-2023
    • (2023)The Learnable Model-Based Genetic Algorithm for the IP Mapping ProblemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321502342:7(2350-2363)Online publication date: 1-Jul-2023
    • (2021)Power Management of Monolithic 3D Manycore Chips with Inter-tier Process VariationsACM Journal on Emerging Technologies in Computing Systems10.1145/343076517:2(1-19)Online publication date: 6-Jan-2021
    • (2020)GPU-accelerated static timing analysisProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415631(1-9)Online publication date: 2-Nov-2020

    View Options

    Login options

    Full Access

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media