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Controller-aware memory coloring for multicore real-time systems

Published: 09 April 2018 Publication History

Abstract

Memory latencies vary in non-uniform memory access (NUMA) systems so that execution times may become unpredictable in a multicore real-time system. This results in overly conservative scheduling with low utilization due to loose bounds on the worst-case execution time (WCET) of tasks. This work contributes a controller/node-aware memory coloring (CAMC) allocator inside the Linux kernel for the entire address space to reduce access conflicts and latencies by isolating tasks from one another. CAMC improves timing predictability and performance over Linux' buddy allocator and prior coloring methods. It provides core isolation with respect to banks and memory controllers for real-time systems. To our knowledge, this work is first to consider multiple memory controllers in real-time systems, combine them with bank coloring, and assess its performance on a NUMA architecture.

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  • (2023)Minimizing Cache Usage for Real-time SystemsProceedings of the 31st International Conference on Real-Time Networks and Systems10.1145/3575757.3593651(200-211)Online publication date: 7-Jun-2023
  • (2023)Co-Optimizing Cache Partitioning and Multi-Core Task Scheduling: Exploit Cache Sensitivity or Not?2023 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS59052.2023.00028(224-236)Online publication date: 5-Dec-2023
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    cover image ACM Conferences
    SAC '18: Proceedings of the 33rd Annual ACM Symposium on Applied Computing
    April 2018
    2327 pages
    ISBN:9781450351911
    DOI:10.1145/3167132
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    Published: 09 April 2018

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    Author Tags

    1. NUMA
    2. memory access
    3. real-time predictability

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    SAC 2018: Symposium on Applied Computing
    April 9 - 13, 2018
    Pau, France

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    Overall Acceptance Rate 1,650 of 6,669 submissions, 25%

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    Cited By

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    • (2024)Minimizing cache usage with fixed-priority and earliest deadline first schedulingReal-Time Systems10.1007/s11241-024-09423-760:4(625-664)Online publication date: 28-Jun-2024
    • (2023)Minimizing Cache Usage for Real-time SystemsProceedings of the 31st International Conference on Real-Time Networks and Systems10.1145/3575757.3593651(200-211)Online publication date: 7-Jun-2023
    • (2023)Co-Optimizing Cache Partitioning and Multi-Core Task Scheduling: Exploit Cache Sensitivity or Not?2023 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS59052.2023.00028(224-236)Online publication date: 5-Dec-2023
    • (2023)A shared libraries aware and bank partitioning-based mechanism for multicore architectureSoft Computing10.1007/s00500-023-08020-327:13(8775-8787)Online publication date: 24-Apr-2023
    • (2022)A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore PlatformsIEEE Access10.1109/ACCESS.2022.315189110(21853-21882)Online publication date: 2022
    • (2021)MUCHProceedings of the 36th Annual ACM Symposium on Applied Computing10.1145/3412841.3441931(511-520)Online publication date: 22-Apr-2021
    • (2021)NUMA-aware memory coloring for multicore real-time systemsJournal of Systems Architecture10.1016/j.sysarc.2021.102188118(102188)Online publication date: Sep-2021
    • (2020)On the reliability of hardware event monitors in MPSoCs for critical domainsProceedings of the 35th Annual ACM Symposium on Applied Computing10.1145/3341105.3373955(580-589)Online publication date: 30-Mar-2020
    • (2020)HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3013051(1-1)Online publication date: 2020

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