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DLibOS: Performance and Protection with a Network-on-Chip

Published: 19 March 2018 Publication History

Abstract

A long body of research work has led to the conjecture that highly efficient IO processing at user-level would necessarily violate protection. In this paper, we debunk this myth by introducing DLibOS a new paradigm that consists of distributing a library OS on specialized cores to achieve performance and protection at the user-level. Its main novelty consists of leveraging network-on-chip to allow hardware message passing, rather than context switches, for communication between different address spaces. To demonstrate the feasibility of our approach, we implement a driver and a network stack at user-level on a Tilera many-core machine. We define a novel asynchronous socket interface and partition the memory such that the reception, the transmission and the application modify isolated regions. Our high performance results of 4.2 and 3.1 million requests per second obtained on a webserver and the Memcached applications, respectively, confirms the relevance of our design decisions. Finally, we compare DLibOS against a non-protected user-level network stack and show that protection comes at a negligible cost.

References

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Berk Atikoglu, Yuehai Xu, Eitan Frachtenberg, Song Jiang, and Mike Paleczny. 2012. Workload Analysis of a Large-scale Key-value Store SIGMETRICS '12. ACM, 53--64.
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Luiz Barroso, Mike Marty, David Patterson, and Parthasarathy Ranganathan. 2017. Attack of the Killer Microseconds. Commun. ACM Vol. 60, 4 (March. 2017), 48--54. http://www.usenix.org/conference/atc16/technical-sessions/presentation/yasukata
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Christopher Zimmer and Frank Mueller. 2015. NoCMsg: A Scalable Message-Passing Abstraction for Network-on-Chips. ACM Trans. Archit. Code Optim. Vol. 12, 1 (March. 2015), 1:1--1:24. 1544--3566

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Published In

cover image ACM Conferences
ASPLOS '18: Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems
March 2018
827 pages
ISBN:9781450349116
DOI:10.1145/3173162
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 53, Issue 2
    ASPLOS '18
    February 2018
    809 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/3296957
    Issue’s Table of Contents
Publication rights licensed to ACM. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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Publication History

Published: 19 March 2018

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Author Tags

  1. latency-critical applications
  2. memory protection
  3. microsecond-scale computing
  4. network-on-chip
  5. performance

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ASPLOS '18

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ASPLOS '18 Paper Acceptance Rate 56 of 319 submissions, 18%;
Overall Acceptance Rate 535 of 2,713 submissions, 20%

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Cited By

View all
  • (2024) Core-Local Reasoning and Predictable Cross-Core Communication with M 3 2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS61025.2024.00024(199-211)Online publication date: 13-May-2024
  • (2022)Towards isolated execution at the machine levelProceedings of the 13th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3546591.3547530(68-77)Online publication date: 23-Aug-2022
  • (2022)Towards practical multikernel OSes with MySySProceedings of the 13th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3546591.3547525(29-37)Online publication date: 23-Aug-2022
  • (2022)Efficient and scalable core multiplexing with M³vProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507741(452-466)Online publication date: 28-Feb-2022
  • (2019)M3XProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358859(617-631)Online publication date: 10-Jul-2019

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