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Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data

Published: 15 February 2018 Publication History

Abstract

The binary number representation has dominated digital logic for decades due to its compact storage requirements. However, since the number system is positional, it needs to "unpack»» bits, perform computations, and repack the bits back to binary (\emphe.g., partial products in multiplication).An alternative representation is the unary number system: we use N bits, out of which the first M are 1 and the rest are 0 to represent the value $M/N$. We present a novel method which first converts binary numbers to unary using thermometer encoders, then uses a "scaling network»» followed by voting gates that we call "alternator logic»», followed by an adder tree to convert the numbers back to the binary format. For monotonically increasing functions, the scaling network is all we need, which essentially uses only the routing resources and flip-flops on the FPGA architecture. Our method is especially well-suited to FPGAs due to the abundant availability of routing and FF resources, and for the ability of FPGAs to realize high fanout gates for highly oscillating functions. We compare our method to stochastic computing and to conventional binary implementations on a number of functions, as well as on two common image processing applications. Our method is clearly superior to the conventional binary implementation: our area×delay cost is on average only 3%, 8% and 32% of the binary method for 8-, 10-, and 12-bit resolutions respectively. Compared to stochastic computing, our cost is 6%, 5%, and 8% for those resolutions. The area cost includes conversions from and to the binary format. Our method out performs the conventional binary method on an edge detection algorithm. However, it is not competitive with the binary method on the median filtering application due to the high cost of generating and saving unary representations of the input pixels.

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        cover image ACM Conferences
        FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
        February 2018
        310 pages
        ISBN:9781450356145
        DOI:10.1145/3174243
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 15 February 2018

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        Author Tags

        1. alternator logic
        2. scaling network
        3. stochastic computin
        4. thermometer code
        5. unary computing

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        • (2023)Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image ProcessingProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573181(165-175)Online publication date: 12-Feb-2023
        • (2023)A Nonlinear Function Logic Computing Architecture With Low Switching ActivityIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.327358870:9(3649-3653)Online publication date: Sep-2023
        • (2023)Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary Computing2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323844(1-7)Online publication date: 28-Oct-2023
        • (2023)Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00020(105-113)Online publication date: May-2023
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        • (2021)Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/349457015:3(1-25)Online publication date: 27-Dec-2021
        • (2021)Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic ComputingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305185640:12(2495-2507)Online publication date: Dec-2021
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