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Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling

Published: 23 February 2018 Publication History

Abstract

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a major challenge to test 2.5D ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this article, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. By considering the trade-off between test-application time, test-power budget, and test quality, the proposed technique provides test schedules with minimum test-application time under constraints on power consumption and fault coverage. Compared to previous work, the proposed technique can reduce test-application time by up to 53.4 for benchmark designs while achieving higher fault coverage. Since the loss in fault coverage due to multicast testing is extremely small, we can use top-off patterns to achieve full fault coverage for the dies at negligible additional cost.

References

[1]
B. Banijamali, S. Ramalingam, K. Nagarajan, and R. Chaware. 2011. Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA. In Proceedings of the Electronic Components and Technology Conference. 285--290.
[2]
M. Bohr. 2009. The new era of scaling in an SoC world. In Proceedings of the International Solid State Circuits Conference. 23--28.
[3]
K. Chakrabarty. 2000. Test scheduling for core-based systems using mixed-integer linear programming. IEEE Trans. Comput.-Aided Des. 19, 10 (2000), 1163--1174.
[4]
C. C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu. 2011a. Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. In Proceedings of IEEE International Test Conference. 1--10.
[5]
C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu. 2011b. Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base. In Proceedings of IEEE Asian Test Symposium. 451--456.
[6]
Y. Deng and W. P. Maly. 2005. 2.5-dimensional VLSI system integration. IEEE Trans. VLSI Syst. 13, 6 (2005), 668--677.
[7]
R. Dorsch, R. H. Rivera, H. J. Wunderlich, and M. Fischer. 2002. Adapting an SoC to ATE concurrent test capabilities. In Proceedings of IEEE International Test Conference. 1169--1175.
[8]
P. Dorsey. 2010. Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency. White paper. Retrieved from http://www.xilinx.com/support/documentation/whitepapers/wp380StackedSiliconInterconnectTechnology.pdf.
[9]
P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H.-J. Wunderlich. 2001. A modified clock scheme for a low power BIST test pattern generator. In Proceedings IEEE VLSI Test Symposium. 306--311.
[10]
S. Y. Huang, L. R. Huang, K. H. Tsai, and W. T. Cheng. 2013. Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. In Proceedings of IEEE International Test Conference. 1--8.
[11]
Y. Huang, W.-T. Cheng, C.-C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan, and S. M. Reddy. 2001. Resource allocation and test scheduling for concurrent test of core-based SOC design. Proc. IEEE Asian Test Symposium (2001), 265--270.
[12]
IEEE Computer Society 2001. IEEE Std 1149.1TM-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE Computer Society, IEEE, New York, NY.
[13]
ITRS. 2015. International Technology Roadmap for Semiconductors, Heterogeneous Integration, 2015. Retrieved from http://www.itrs.net/.
[14]
V. Iyengar and K. Chakrabarty. 2002. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE Trans. Comput.-Aided Des. 21, 9 (2002), 1088--1094.
[15]
M. Jackson. 2012. A silicon interposer-based 2.5 D-IC design flow, going 3D by evolution rather than by revolution. Synop. Insight Newsl., Tech. Rep. 1 (2012).
[16]
P. K. D. Jagannadha, M. Yilmaz, M. Sonawane, S. Chadalavada, S. Sarangi, B. Bhaskaran, and A. Abdollahian. 2016. Advanced test methodology for complex SoCs. In Proceedings of IEEE International Test Conference. 1--10.
[17]
J. H. Jiang, W.-B. Jone, S.-C. Chang, and S. Ghosh. 2003. Embedded core test generation using broadcast test architecture and netlist scrambling. IEEE Trans. Reliab. 52, 4 (2003), 435--443.
[18]
G. John. 2015. Test Flow for Advanced Packages (2.5 D/SLIM/3D). White paper. Retrieved from http://www.circuitnet.com/articles/111078.html.
[19]
H. H. Jones. 2010. Technical Viability of Stacked Silicon Interconnect Technology. Xilinx. White paper. Retrieced from http://www.xilinx.com/publications/technology/stacked-siliconinterconnect-technology-ibs-research.pdf.
[20]
H. Jun, S. Nam, H. Jin, J. C. Lee, Y. J. Park, and J. J. Lee. 2017. High-bandwidth memory (HBM) test challenges and solutions. IEEE Des. Test Comput. 34, 1 (2017), 16--25.
[21]
S. Koranne. 2002. On test scheduling for core-based SOCs. In Proceedings of IEEE Asia South Pacific Design Automation Conference. 505.
[22]
K. Kumagai, Y. Yoneda, H. Izumino, H. Shimojo, M. Sunohara, T. Kurihara, M. Higashi, and Y. Mabuchi. 2008. A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect. In Proceedings of the Electronic Components and Technology Conference. 571--576.
[23]
A. Larsson. 2008. Test Optimization for Core-Based System-on-Chip. Ph.D. Dissertation. Linkoping University.
[24]
E. Larsson, K. Arvidsson, H. Fujiwara, and Z. Peng. 2004. Efficient test solutions for core-based designs. IEEE Trans. Comput.-Aided Des. 23, 5 (2004), 758--775.
[25]
K. J. Lee, J. J. Chen, and C. H. Huang. 1998. Using a single input to support multiple scan chains. In Proceedings of the International Conference on Computer-Aided Design. 74--78.
[26]
X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli. 2003. High-frequency, at-speed scan testing. IEEE Des. Test Comput. 20, 5 (2003), 17--25.
[27]
Y. Liu, M. Li, M. Jiang, D. W. Kim, S. Gu, and K. N. Tu. 2016. Joule heating enhanced electromigration failure in redistribution layer in 2.5D IC. In Proceedings of the Electronic Components and Technology Conference. 1359--1363.
[28]
E. J. Marinissen. 2012. Challenges and emerging solutions in testing TSV-based 2 1/2D-and 3D-stacked ICs. In Proceedings of Design, Automation, and Test in Europe. 1277--1282.
[29]
E. J. Marinissen, T. McLaurin, and H. Jiao. 2016. IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. In Proceedings of IEEE European Test Symposium. 1--10.
[30]
K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, and S. Kajihara. 2008. Effective IR-drop reduction in at-speed scan testing using distribution-controlling X-identification. In Proceedings of the International Conference on Computer-Aided Design. 52--58.
[31]
J. Nyathi, S. Sarkar, and P. P. Pande. 2007. Multiple clock domain synchronization for network on chip architectures. In Proceedings of IEEE International Conference on SOC. 291--294.
[32]
J. Pouget, E. Larsson, and Z. Peng. 2003. SOC test time minimization under multiple constraints. In Proceedings of IEEE Asian Test Symposium. 312--317.
[33]
R. Radojcic. 2017. More-than-Moore 2.5 D and 3D SiP Integration. Springer.
[34]
J. Rearick. 2015. Testing the AMD FIJI GPU in the 3rd dimension. Keynote Speech, ITC 3D Test Workshop (2015).
[35]
M. Sunohara, T. Tokunaga, T. Kurihara, and M. Higashi. 2008. Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring. In Proceedings of the Electronic Components and Technology Conference. 847--852.
[36]
SynTest. 2008. TurboBISTTM-Logic Logic BIST Tool Suite. Retrieved from http://www.syntest.com/ProdDataSheet/TBISTLOGIC-datasheet081502a.pdf.
[37]
M. J. Wang, C. Y. Hung, C. L. Kao, P. N. Lee, C. H. Chen, C. P. Hung, and H. M. Tong. 2012. TSV technology for 2.5D IC solution. In Proceedings of the Electronic Components and Technology Conference. 284--288.
[38]
R. Wang, B. Bhaskaran, K. Natarajan, A. Abdollahian, K. Narayanun, K. Chakrabarty, and A. Sanghani. 2016a. A programmable method for low-power scan shift in SoC integrated circuits. In Proceedings IEEE VLSI Test Symposium. 1--6.
[39]
R. Wang, K. Chakrabarty, and S. Bhawmik. 2015a. Interconnect testing and test-path scheduling for interposer-based 2.5-D ICs. IEEE Trans. Comput.-Aided Des. 34, 1 (2015), 136--149.
[40]
R. Wang, K. Chakrabarty, and S. Bhawmik. 2015b. Built-in self-test and test scheduling for interposer-based 2.5D IC. ACM Trans. Des. Autom. Electron. Syst. 20, 4 (2015), 58.
[41]
R. Wang, K. Chakrabarty, and B. Eklow. 2014. Scan-based testing of post-bond silicon interposer interconnects in 2.5-D ICs. IEEE Trans. Comput.-Aided Des. 33, 9 (2014), 1410--1423.
[42]
R. Wang, G. Li, R. Li, J. Qiang, and K. Chakrabarty. 2017. ExTest scheduling and optimization for 2.5D SoCs with wrapped tiles. IEEE Trans. Comput.-Aided Des. 36, 6 (2017), 1030--1042.
[43]
R. Wang, Z. Li, S. Kannan, and K. Chakrabarty. 2016b. Pre-bond testing of the silicon interposer in 2.5D ICs. In Proceedings of Design, Automation, and Test in Europe. 978--983.
[44]
P. Wohl, J. A. Waicukauski, J. E. Colburn, and M. Sonawane. 2014. Achieving extreme scan compression for SoC designs. In Proceedings of IEEE International Test Conference. 1--8.
[45]
Q. Xu and N. Nicolici. 2005. Resource-constrained system-on-a-chip test: A survey. IEE Proc., Comput. Digital Tech. 152, 1 (2005), 67--81.
[46]
G. Zeng and H. Ito. 2006. Concurrent core test for SOC using shared test set and scan chain disable. In Proceedings of Design, Automation, and Test in Europe. European Design and Automation Association 3001 Leuven, Belgium, 1045--1050.
[47]
X. Zhang, J. K. Lin, S. Wickramanayaka, S. Zhang, R. Weerasekera, R. Dutta, K. F. Chang, K.-J. Chui, H. Y. Li, and David S. Wee H. 2015. Heterogeneous 2.5D integration on through silicon interposer. Appl. Phys. Rev. 2, 2 (2015), 021308.
[48]
Q. Zhou and K. J. Balakrishnan. 2007. Test cost reduction for SoC using a combined approach to test data compression and test scheduling. In Proceedings of Design, Automation, and Test in Europe. 39--44.
[49]
W. Zou, S. M. Reddy, I. Pomeranz, and Y. Huang. 2003. SOC test scheduling using simulated annealing. In Proceedings IEEE VLSI Test Symposium. 325--330.

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  • (2025)Thermal Characteristics Analysis and Optimization of Heterogeneous 2.5-D Package Under System-Level ConditionsIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2024.346727415:1(157-164)Online publication date: Jan-2025
  • (2020)Boundary scan based interconnect testing design for silicon interposer in 2.5D ICsIntegration, the VLSI Journal10.1016/j.vlsi.2020.02.00672:C(171-182)Online publication date: 1-May-2020

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 23, Issue 3
    May 2018
    341 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/3184476
    • Editor:
    • Naehyuck Chang
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 23 February 2018
    Accepted: 01 December 2017
    Revised: 01 November 2017
    Received: 01 July 2017
    Published in TODAES Volume 23, Issue 3

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    Author Tags

    1. 2.5D IC
    2. multicast
    3. silicon interposer
    4. test scheduling

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    • (2025)Thermal Characteristics Analysis and Optimization of Heterogeneous 2.5-D Package Under System-Level ConditionsIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2024.346727415:1(157-164)Online publication date: Jan-2025
    • (2020)Boundary scan based interconnect testing design for silicon interposer in 2.5D ICsIntegration, the VLSI Journal10.1016/j.vlsi.2020.02.00672:C(171-182)Online publication date: 1-May-2020

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