research-article

Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors

Authors:

Ashwini A. Kulkarni,

Shounak Chakraborty,

Shrinivas P. Mahajan,

Hemangee K. KapoorAuthors Info & Claims

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

Pages 249 - 254

https://doi.org/10.1145/3194554.3194581

Published: 30 May 2018 Publication History

Abstract

Heavy leakage power consumption of on-chip last level caches (LLCs) has become the primary obstacle for architecting chip multi-processors (CMPs) in recent times. As leakage power has a direct relationship with the supply voltage, hence, periodic access profile based dynamic voltage scaling (DVS) in the LLC banks can be a promising option towards reducing this heavy cache leakage. A plethora of prior attempts have reduced this by anticipating working set size (WSS) of the applications and eventually putting some portions of the cache banks in low power mode. This proposed work aims to reduce leakage by putting a whole LLC bank into a low power (snoozy) mode through exploiting DVS at cache banks having minimal usages. Additionally, the resulting performance impacts of the low power snoozy mode are alleviated further by putting some snoozy banks in active mode on-demand. Experimental evaluations using full system simulation on a multi-banked 2MB 8-way set associative L2 cache show 10% more leakage savings on an average over a prior drowsy technique.

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Cited By

Kulkarni AJoshi CRani KAgarwal SMahajan SKapoor H(2018)Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors2018 8th International Symposium on Embedded Computing and System Design (ISED)10.1109/ISED.2018.8704045(230-235)Online publication date: Dec-2018
https://doi.org/10.1109/ISED.2018.8704045

Index Terms

Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multicore architectures
2. Hardware
  1. Power and energy
    1. Power estimation and optimization

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Published In

cover image ACM Conferences

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

May 2018

533 pages

ISBN:9781450357241

DOI:10.1145/3194554

General Chair:
Deming Chen
University of Illinois, USA
,
Program Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA

Copyright © 2018 ACM.

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Published: 30 May 2018

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GLSVLSI '18: Great Lakes Symposium on VLSI 2018

May 23 - 25, 2018

IL, Chicago, USA

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GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Kulkarni AJoshi CRani KAgarwal SMahajan SKapoor H(2018)Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors2018 8th International Symposium on Embedded Computing and System Design (ISED)10.1109/ISED.2018.8704045(230-235)Online publication date: Dec-2018
https://doi.org/10.1109/ISED.2018.8704045

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