research-article

A machine learning framework to identify detailed routing short violations from a placed netlist

Authors:

Aysa Fakheri Tabrizi,

Nima Karimpour Darav,

Ismail Bustany,

Andrew Kennings,

Laleh BehjatAuthors Info & Claims

DAC '18: Proceedings of the 55th Annual Design Automation Conference

Article No.: 48, Pages 1 - 6

https://doi.org/10.1145/3195970.3195975

Published: 24 June 2018 Publication History

Abstract

Detecting and preventing routing violations has become a critical issue in physical design, especially in the early stages. Lack of correlation between global and detailed routing congestion estimations and the long runtime required to frequently consult a global router adds to the problem. In this paper, we propose a machine learning framework to predict detailed routing short violations from a placed netlist. Factors contributing to routing violations are determined and a supervised neural network model is implemented to detect these violations. Experimental results show that the proposed method is able to predict on average 90% of the shorts with only 7% false alarms and considerably reduced computational time.

References

[1]

M. Abadi and et all. 2015. TensorFlow: Large-Scale Machine Learning on Heterogeneous Systems. (2015). https://www.tensorflow.org/ Software available from tensorflow.org.

[2]

I. Bustany, D. Chinnery, J. Shinnerl, and V. Yutsi. 2015. ISPD 2015 benchmarks with fence regions and routing blockages for detailed-routing-driven placement. In ISPD '15. 157--164.

Digital Library

[3]

W. J. Chan, P. Ho, A. B. Kahng, and P. Saxena. 2017. Routability Optimization for Industrial Designs at Sub-14Nm Process Nodes Using Machine Learning. In ISPD '17. 15--21.

Digital Library

[4]

Y. Chang, Y. Lee, and T. Wang. 2008. NTHU-Route 2.0: A Fast and Stable Global Router. In ICCAD '08. 338--343.

Digital Library

[5]

N. Chawla, N. Japkowicz, and A. Kotcz. 2004. Editorial: Special Issue on Learning from Imbalanced Data Sets. SIGKDD Explor. Newsl. 6, 1 (June 2004), 1--6.

Digital Library

[6]

H. He and E. A. Garcia. 2009. Learning from Imbalanced Data. IEEE Trans. on Knowl. and Data Eng. 21, 9 (Sept. 2009), 1263--1284.

Digital Library

[7]

ISPD15. 2015. ISPD 2015 Blockage-Aware Detailed Routing-Driven Placement Contest. http://www.ispd.cc/contests/15/ispd2015_contest.html. (2015). Accessed: 2018-04-04.

[8]

N. Karimpour Darav, A. Kennings, A. Tabrizi, D. Westwick, and L. Behjat. 2016. Eh?Placer: A High-Performance Modern Technology-Driven Placer. ACM TODAES 21, 3 (2016), 37:1--37:27.

Digital Library

[9]

D. P. Kingma and J. Ba. 2014. Adam: A Method for Stochastic Optimization. CoRR abs/1412.6980 (2014).

[10]

J. Lou, S. Krishnamoorthy, and H. S. Sheng. 2001. Estimating Routing Congestion Using Probabilistic Analysis. In ISPD '01. 112--117.

Digital Library

[11]

Mentor Graphics, Inc. 2015. Olympus-SoC place and route for advanced node designs. Technical Report. www.mentor.com/products/ic_nanometer_design/place-route/olympus-soc.

[12]

M. Pan and C. Chu. 2007. IPR: An Integrated Placement and Routing Algorithm. In DAC '07. 59--62.

Digital Library

[13]

Z. Qi, Y. Cai, and Q. Zhou. 2014. Accurate prediction of detailed routing congestion using supervised data learning. In ICCAD '14. 97--103.

[14]

J. Roy, N. Viswanathan, G. Nam, C. Alpert, and I. Markov. 2009. CRISP: Congestion Reduction by Iterated Spreading During Placement. In ICCAD '09. 357--362.

Digital Library

[15]

C. Seiffert, T. M. Khoshgoftaar, J. Van Hulse, and A. Napolitano. 2010. RUSBoost: A Hybrid Approach to Alleviating Class Imbalance. Trans. Sys. Man Cyber. Part A 40, 1 (Jan. 2010), 185--197.

Digital Library

[16]

D. Shi and A. Davoodi. 2017. TraPL: Track Planning of Local Congestion for Global Routing. In DAC '17. 19:1--19:6.

Digital Library

[17]

H. Shojaei, A. Davoodi, and J. Linderoth. 2013. Planning for Local Net Congestion in Global Routing. In ISPD '13. 85--92.

Digital Library

[18]

H. Shojaei, A. Davoodi, and J. T. Linderoth. 2011. Congestion Analysis for Global Routing via Integer Programming. In ICCAD '11. 256--262.

Digital Library

[19]

A. Tabrizi, N. Darav, L. Rakai, A. Kennings, and L. Behjat. 2017. Detailed routing violation prediction during placement using machine learning. In VLSI-DAT. 1--4.

[20]

A. Tabrizi, N. Darav, L. Rakai, A. Kennings, W. Swartz, and L. Behjat. 2015. A Detailed Routing-Aware Detailed Placement Technique. In ISVLSI '15. 38--43.

[21]

J. Andres Torres. 2012. ICCAD-2012 CAD Contest in Fuzzy Pattern Matching for Physical Verification and Benchmark Suite. In ICCAD '12. 349--350.

Digital Library

[22]

L. Wang. 2017. Experience of Data Analytics in EDA and Test - Principles, Promises, and Challenges. Trans. Comp.-Aided Des. Integ. Cir. Sys. 36, 6 (June 2017), 885--898.

Digital Library

[23]

L. Wang, P. Bastani, and M. Abadir. 2007. Design-silicon Timing Correlation: A Data Mining Perspective. In DAC '07. 384--389.

Digital Library

[24]

Y. Wei and et. all. 2012. GLARE: Global and Local Wiring Aware Routability Evaluation. In DAC '12. 768--773.

Digital Library

[25]

Jurjen Westra, Chris Bartels, and Patrick Groeneveld. 2004. Probabilistic Congestion Prediction. In ISPD. 204--209.

Digital Library

[26]

J. Westra and P. Groeneveld. 2005. Is Probabilistic Congestion Estimation Worthwhile?. In SLIP '05. 99--106.

Digital Library

[27]

D. Wolpert. 1996. The Lack of A Priori Distinctions Between Learning Algorithms. Neural Computation 8, 7 (1996), 1341--1390.

Digital Library

[28]

Y. Xu, Y. Zhang, and Ch. Chu. 2009. FastRoute 4.0: Global Router with Efficient via Minimization. In ASPDAC '09. 576--581.

Digital Library

[29]

Y. Yu, G. Lin, I. Jiang, and C. Chiang. 2013. Machine-learning-based Hotspot Detection Using Topological Classification and Critical Feature Extraction. In DAC '13. 67:1--67:6.

Digital Library

[30]

Q. Zhou, X. Wang, Z. Qi, Z. Chen, Q. Zhou, and Y. Cai. 2015. An accurate detailed routing routability prediction model in placement. In ASQED '15. 119--122.

Cited By

Lin JLin WLiang SGao PXing YWu TXiong XCai S(2024)An Efficient Method of DRC Violation Prediction with a Serial Deep Learning ModelACM Transactions on Design Automation of Electronic Systems10.1145/369496829:6(1-16)Online publication date: 5-Sep-2024
https://dl.acm.org/doi/10.1145/3694968
Lin JChen YYang YHung WTsai CFu DChao MThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural NetworkProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590216(313-319)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590216
Krishna Kashyap SOzev S(2023)IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design StagesACM Transactions on Design Automation of Electronic Systems10.1145/357254628:4(1-23)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3572546
Show More Cited By

Index Terms

A machine learning framework to identify detailed routing short violations from a placed netlist
1. Computing methodologies
  1. Machine learning
    1. Learning paradigms
      1. Supervised learning
        Supervised learning by classification
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

Recommendations

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs

In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates. Based on binary trees, the MP-tree is very efficient, effective, and ...
Seeing the forest and the trees: Steiner wirelength optimization in placemen
ISPD '06: Proceedings of the 2006 international symposium on Physical design

We show how to optimize Steiner-tree Wirelength (StWL) in global and detail placement without a significant runtime penalty, making the use of Half-Perimeter Wirelength unnecessary. Given that StWL correlates with Routed Wirelength (rWL) much better ...
A Robust Mixed-Size Legalization and Detailed Placement Algorithm

Placement is one of the most important steps in the RTL-to-GDSII synthesis process as it directly defines the interconnects. The rapid increase in IC design complexity and the widespread use of intellectual-property blocks have made the so-called mixed-...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '18: Proceedings of the 55th Annual Design Automation Conference

June 2018

1089 pages

ISBN:9781450357005

DOI:10.1145/3195970

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 June 2018

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DAC '18

Sponsor:

EDAC
SIGDA

DAC '18: The 55th Annual Design Automation Conference 2018

June 24 - 29, 2018

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

18
Total Citations
View Citations
753
Total Downloads

Downloads (Last 12 months)37
Downloads (Last 6 weeks)6

Reflects downloads up to 03 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Lin JLin WLiang SGao PXing YWu TXiong XCai S(2024)An Efficient Method of DRC Violation Prediction with a Serial Deep Learning ModelACM Transactions on Design Automation of Electronic Systems10.1145/369496829:6(1-16)Online publication date: 5-Sep-2024
https://dl.acm.org/doi/10.1145/3694968
Lin JChen YYang YHung WTsai CFu DChao MThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural NetworkProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590216(313-319)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590216
Krishna Kashyap SOzev S(2023)IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design StagesACM Transactions on Design Automation of Electronic Systems10.1145/357254628:4(1-23)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3572546
Utyamishev DPartin-Vaisband I(2023)Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural NetworksACM Transactions on Design Automation of Electronic Systems10.1145/356493028:4(1-19)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3564930
Park SKim DKwon SKang S(2023)Routability Prediction and Optimization Using Explainable AI2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323630(1-8)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323630
Chen YSu MDing HWeng SLin ZBai X(2023)High-correlation 3D routability estimation for congestion-guided global routingThe Journal of Supercomputing10.1007/s11227-023-05553-080:3(3114-3141)Online publication date: 29-Aug-2023
https://doi.org/10.1007/s11227-023-05553-0
Melikyan VMelikyan V(2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
https://doi.org/10.1007/978-3-031-50714-4_6
Wu NXie Y(2022)A Survey of Machine Learning for Computer Architecture and SystemsACM Computing Surveys10.1145/349452355:3(1-39)Online publication date: 3-Feb-2022
https://dl.acm.org/doi/10.1145/3494523
Liang RXiang HPandey DReddy LRamji SNam GHu J(2022)Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312667641:10(3503-3514)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3126676
Netto RFabre SFontana TLivramento VPilla LBehjat LGuntzel J(2022)Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307912641:5(1481-1494)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3079126
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten