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Cache side-channel attacks and time-predictability in high-performance critical real-time systems

Published: 24 June 2018 Publication History

Abstract

Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous requirements in embedded computers, and automotive is not an exception to that. In this paper we analyze time-predictability (as an example of safety concern) and side-channel attacks (as an example of security issue) in cache memories. While injecting randomization in cache timing-behavior addresses each of those concerns separately, we show that randomization solutions for time-predictability do not protect against side-channel attacks and vice-versa. We then propose a randomization solution to achieve both safety and security goals.

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Cited By

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  • (2024)Timing Side-Channel Attacks and Countermeasures in CPU MicroarchitecturesACM Computing Surveys10.1145/3645109Online publication date: 7-Feb-2024
  • (2024)Safe and Secure? On the Timing Analysability of Cryptographic Implementations2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS61025.2024.00014(68-80)Online publication date: 13-May-2024
  • (2024)Enterprise-Class Cache Compression Design2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00080(996-1011)Online publication date: 2-Mar-2024
  • Show More Cited By

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cover image ACM Conferences
DAC '18: Proceedings of the 55th Annual Design Automation Conference
June 2018
1089 pages
ISBN:9781450357005
DOI:10.1145/3195970
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 24 June 2018

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Author Tags

  1. cache
  2. probabilistic analysis
  3. randomization
  4. side-channel attacks

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  • Research-article

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  • Spanish Ministry of Science and Innovation

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DAC '18
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DAC '18: The 55th Annual Design Automation Conference 2018
June 24 - 29, 2018
California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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June 22 - 26, 2025
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Cited By

View all
  • (2024)Timing Side-Channel Attacks and Countermeasures in CPU MicroarchitecturesACM Computing Surveys10.1145/3645109Online publication date: 7-Feb-2024
  • (2024)Safe and Secure? On the Timing Analysability of Cryptographic Implementations2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS61025.2024.00014(68-80)Online publication date: 13-May-2024
  • (2024)Enterprise-Class Cache Compression Design2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00080(996-1011)Online publication date: 2-Mar-2024
  • (2023)Scatter and Split Securely: Defeating Cache Contention and Occupancy Attacks2023 IEEE Symposium on Security and Privacy (SP)10.1109/SP46215.2023.10179440(2273-2287)Online publication date: May-2023
  • (2023)SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations2023 IEEE 8th European Symposium on Security and Privacy (EuroS&P)10.1109/EuroSP57164.2023.00044(631-650)Online publication date: Jul-2023
  • (2022)Under the Dome: Preventing Hardware Timing Information LeakageSmart Card Research and Advanced Applications10.1007/978-3-030-97348-3_13(233-253)Online publication date: 9-Mar-2022
  • (2021)Security and Reliability of Safety-Critical RTOSSN Computer Science10.1007/s42979-021-00753-y2:5Online publication date: 25-Jun-2021
  • (2021)Introduction to Hardware Security for FPGA Based SystemsSelf Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms10.1007/978-3-030-79701-0_4(69-89)Online publication date: 24-Aug-2021
  • (2020)CHASM: Security Evaluation of Cache Mapping SchemesEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-60939-9_17(245-261)Online publication date: 7-Oct-2020
  • (2019)SCATTERCACHEProceedings of the 28th USENIX Conference on Security Symposium10.5555/3361338.3361385(675-692)Online publication date: 14-Aug-2019

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