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Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems

Published: 24 June 2018 Publication History

Abstract

DRAM memory access is a critical performance bottleneck. To access one cache block, an entire row needs to be sensed and amplified, data restored into the bitcells and the bitlines precharged, incurring high latency. Isolating the bitlines and sense amplifiers after activation enables reads and precharges to happen in parallel. However, there are challenges in achieving this isolation. We tackle these challenges and propose an effective scheme, simultaneous read and precharge (SRP), to isolate the sense amplifiers and bitlines and serve reads and precharges in parallel. Our detailed architecture and circuit simulations demonstrate that our simultaneous read and precharge (SRP) mechanism is able to achieve an 8.6% performance benefit over baseline, while reducing sense amplifier idle power by 30%, as compared to prior work, over a wide range of workloads.

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Cited By

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  • (2024)FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed RestorationACM Transactions on Architecture and Code Optimization10.1145/364945521:2(1-27)Online publication date: 21-May-2024
  • (2023)Low-Power Single Bitline Load Sense Amplifier for DRAMElectronics10.3390/electronics1219402412:19(4024)Online publication date: 25-Sep-2023
  • (2021)PF-DRAMProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00019(126-138)Online publication date: 14-Jun-2021

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cover image ACM Conferences
DAC '18: Proceedings of the 55th Annual Design Automation Conference
June 2018
1089 pages
ISBN:9781450357005
DOI:10.1145/3195970
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 24 June 2018

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DAC '18: The 55th Annual Design Automation Conference 2018
June 24 - 29, 2018
California, San Francisco

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Cited By

View all
  • (2024)FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed RestorationACM Transactions on Architecture and Code Optimization10.1145/364945521:2(1-27)Online publication date: 21-May-2024
  • (2023)Low-Power Single Bitline Load Sense Amplifier for DRAMElectronics10.3390/electronics1219402412:19(4024)Online publication date: 25-Sep-2023
  • (2021)PF-DRAMProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00019(126-138)Online publication date: 14-Jun-2021

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