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Efficient batch statistical error estimation for iterative multi-level approximate logic synthesis

Published: 24 June 2018 Publication History

Abstract

Approximate computing is an emerging energy-efficient paradigm for error-resilient applications. Approximate logic synthesis (ALS) is an important field of it. To improve the existing ALS flows, one key issue is to derive a more accurate and efficient batch error estimation technique for all approximate transformations under consideration. In this work, we propose a novel batch error estimation method based on Monte Carlo simulation and local change propagation. It is generally applicable to any statistical error measurement such as error rate and average error magnitude. We applied the technique to an existing state-of-the-art ALS approach and demonstrated its effectiveness in deriving better approximate circuits.

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  • (2025)Approximate synthesis for LUT count reduction via probabilistic error propagationit - Information Technology10.1515/itit-2024-0074Online publication date: 17-Feb-2025
  • (2022)Dynamically-Tunable Dataflow Architectures Based on Markov Queuing ModelsElectronics10.3390/electronics1104055511:4(555)Online publication date: 12-Feb-2022
  • (2022)Probability-Based DSE of Approximated LUT-Based FPGA Designs2022 IEEE 15th Dallas Circuit And System Conference (DCAS)10.1109/DCAS53974.2022.9845591(1-5)Online publication date: 17-Jun-2022
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    cover image ACM Conferences
    DAC '18: Proceedings of the 55th Annual Design Automation Conference
    June 2018
    1089 pages
    ISBN:9781450357005
    DOI:10.1145/3195970
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 24 June 2018

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    Author Tags

    1. approximate computing
    2. approximate logic synthesis
    3. error estimation
    4. logic synthesis

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    DAC '18: The 55th Annual Design Automation Conference 2018
    June 24 - 29, 2018
    California, San Francisco

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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2025)Approximate synthesis for LUT count reduction via probabilistic error propagationit - Information Technology10.1515/itit-2024-0074Online publication date: 17-Feb-2025
    • (2022)Dynamically-Tunable Dataflow Architectures Based on Markov Queuing ModelsElectronics10.3390/electronics1104055511:4(555)Online publication date: 12-Feb-2022
    • (2022)Probability-Based DSE of Approximated LUT-Based FPGA Designs2022 IEEE 15th Dallas Circuit And System Conference (DCAS)10.1109/DCAS53974.2022.9845591(1-5)Online publication date: 17-Jun-2022
    • (2019)Partition and PropagateProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317878(1-6)Online publication date: 2-Jun-2019

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