ABSTRACT
With increasing design complexity and robustness requirement, analog and mixed-signal (AMS) verification manifests itself as a key bottleneck. While formal methods and machine learning have been proposed for AMS verification, these two techniques suffer from their own limitations, with the former being specifically limited by scalability and the latter by the inherent uncertainty in learning-based models. We present a new direction in AMS verification by proposing a hybrid formal/machine-learning verification technique (HFMV) to combine the best of the two worlds. HFMV adds formalism on the top of a probabilistic learning model while providing a sense of coverage for extremely rare failure detection. HFMV intelligently and iteratively reduces uncertainty of the learning model by a proposed formally-guided active learning strategy and discovers potential rare failure regions in complex high-dimensional parameter spaces. It leads to reliable failure prediction in the case of a failing circuit, or a high-confidence pass decision in the case of a good circuit. We demonstrate that HFMV is able to employ a modest amount of data to identify hard-to-find rare failures which are completely missed by state-of-the-art sampling methods even with high volume sampling data.
- H. Chang and K. Kundert. 2007. Verification of Complex Analog and RF IC Designs. Proc. IEEE 95, 3 (March 2007), 622--639.Google ScholarCross Ref
- H. A. Chipman, E. I. George, and R. E. Mcculloch. 2010. BART: Bayesian Additive Regression Trees. Annals of Applied Statistics 4, 1 (2010), 266--298.Google ScholarCross Ref
- W. Denman, B. Akbarpour, S. Tahar, M. H. Zaki, and L. C. Paulson. 2009. Formal verification of analog designs using MetiTarski. In Formal Methods in Computer-Aided Design (FMCAD). 93--100.Google Scholar
- J. A. Kumar, S. N. Ahmadyan, and S. Vasudevan. 2014. Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, 6 (June 2014), 945--958.Google ScholarCross Ref
- H. Lin, A. M. Khan, and P. Li. 2017. Statistical circuit performance dependency analysis via sparse relevance kernel machine. In IEEE International Conference on IC Design and Technology (ICICDT). 1--4.Google Scholar
- M. Miller and F. Brewer. 2013. Formal verification of analog circuit parameters across variation utilizing SAT. In Design, Automation Test in Europe Conference Exhibition (DATE). 1442--1447. Google ScholarDigital Library
- L. D. Moura and N. Bjørner. 2008. Z3: An Efficient SMT Solver. In Proceedings of the International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS). 337--340. Google ScholarDigital Library
- L. D. Moura, B. Dutertre, and N. Shankar. 2007. A Tutorial on Satisiability Modulo Theories. In Proceedings of the International Conference on Computer Aided Verification (CAV). 20--36. Google ScholarDigital Library
- M. Rana, R. Canal, J. Han, and B. Cockburn. 2016. SRAM memory margin probability failure estimation using Gaussian Process regression. In IEEE 34th International Conference on Computer Design (ICCD). 448--451.Google Scholar
- K. Scheibler, F. Neubauer, A. Mahdi, M. Fränzle, T. Teige, T. Bienmüller, D. Fehrer, and B. Becker. 2016. Accurate ICP-based floating-point reasoning. In Formal Methods in Computer-Aided Design (FMCAD). 177--184. Google ScholarDigital Library
- S. Sun, X. Li, H. Liu, K. Luo, and B. Gu. 2015. Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 7 (July 2015), 1096--1109.Google ScholarDigital Library
- M. E. Tipping. 2001. Sparse Bayesian Learning and the Relevance Vector Machine. Journal of Machine Learning Research 1 (June 2001), 211--244. Google ScholarDigital Library
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