skip to main content
research-article
Public Access

Write Energy Reduction for PCM via Pumping Efficiency Improvement

Published: 26 November 2018 Publication History

Abstract

The emerging Phase Change Memory (PCM) is considered to be a promising candidate to replace DRAM as the next generation main memory due to its higher scalability and lower leakage power. However, the high write power consumption has become a major challenge in adopting PCM as main memory. In addition to the fact that writing to PCM cells requires high write current and voltage, current loss in the charge pumps also contributes a large percentage of high power consumption. The pumping efficiency of a PCM chip is a concave function of the write current. Leveraging the characteristics of the concave function, the overall pumping efficiency can be improved if the write current is uniform. In this article, we propose a peak-to-average (PTA) write scheme, which smooths the write current fluctuation by regrouping write units. In particular, we calculate the current requirements for each write unit by their values when they are evicted from the last level cache (LLC). When the write units are waiting in the memory controller, we regroup the write units by LLC-assisted PTA to reach the current-uniform goal. Experimental results show that LLC-assisted PTA achieved 13.4% of overall energy saving compared to the baseline.

References

[1]
M. Binkert. 2011. The gem5 simulator. ACM SIGARCH Comput. Architect. News 39, 2 (2011), 1--7.
[2]
Sangyeun Cho and Hyunjin Lee. 2009. Flip-N-write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’09). 347--357.
[3]
Youngdon Choi, Ickhyun Song, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Duckmin Kwon, Jung Sunwoo et al. 2012. A 20nm 1.8 V 8Gb PRAM with 40MB/s program bandwidth. In Proceedings of the IEEE International Solid-State Circuits Conference. 46--48.
[4]
Alexandre P. Ferreira, Miao Zhou, Santiago Bock, Bruce Childers, Rami Melhem, and Daniel Mossé. 2010. Increasing PCM main memory lifetime. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’10). 914--919.
[5]
Alexandre P. Ferreira, Miao Zhou, Santiago Bock, Bruce Childers, Rami Melhem, and Daniel Mossé. 2013. Reducing writes in phase-change memory environments by using efficient cache replacement policies. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13). 93--96.
[6]
Matthew R. Guthaus, Jeffrey S. Ringenberg, Dan Ernst, Todd M. Austin, and Richard B. Mudge, Trevor andf Brown. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE International Workshop on Workload Characterization (WWC’01). 3--14.
[7]
Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, and Edwin H.-M. Sha. 2013. Write activity reduction on non-volatile main memories for embedded chip multiprocessors. ACM Trans. Embed. Comput. Syst. 12, 3 (2013), 77.
[8]
Lei Jiang, Youtao Zhang, Bruce R. Childers, and Jun Yang. 2012. FPB: Fine-grained power budgeting to improve write throughput of multi-level cell phase change memory. In Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’12). 1--12.
[9]
Lei Jiang, Bo Zhao, Jun Yang, and Youtao Zhang. 2014. A low power and reliable charge pump design for phase change memories. In Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture (ISCA’14). 397--408.
[10]
Madhura Joshi, Wangyuan Zhang, and Tao Li. 2011. Mercury: A fast and energy-efficient multi-level cell based phase change memory system. In Proceedings of the IEEE 17th International Symposium on High Performance Computer Architecture (HPCA’11). 345--356.
[11]
Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting phase change memory as a scalable dram alternative. ACM SIGARCH Comput. Architect. News 37, 3 (2009), 2--13.
[12]
Kwang-Jin Lee, Beak-Hyung Cho, Woo-Yeong Cho, Sangbeom Kang, Byung-Gil Choi, Hyung-Rok Oh, Chang-Soo Lee, Hye-Jin Kim, Joon-Min Park, Qi Wang et al. 2008. A 90nm 1.8 V 512Mb diode-switch PRAM with 266MB/s read throughput. IEEE J. Solid-State Circ. 43, 1 (2008), 150--162.
[13]
Huizhang Luo, Jingtong Hu, Liang Shi, Chun Jason Xue, and Qingfeng Zhuge. 2016. Peak-to-average pumping efficiency improvement for charge pump in phase change memories. In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC’16). 450--455.
[14]
Prashant J. Nair, Chiachen Chou, Bipin Rajendran, and Moinuddin K. Qureshi. 2015. Reducing read latency of phase change memory via early read and turbo read. In Proceedings of the IEEE 21st International Symposium on High Performance Computer Architecture (HPCA’15). 309--319.
[15]
Xi Zhang, Qian Hu, Dongsheng Wang, Chongmin Li, and Haixia Wang. 2011. A read-write aware replacement policy for phase change memory. In Proceedings of the International Workshop on Advanced Parallel Processing Technologies (APPT’11). Springer, 31--45.
[16]
Poovaiah M. Palangappa and Kartik Mohanram. 2016. CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM. In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA’16). 90--101.
[17]
Gaetano Palumbo and Domenico Pappalardo. 2010. Charge pump circuits: An overview on design strategies and topologies. IEEE Circ. Syst. Mag. 10, 1 (2010), 31--45.
[18]
G. Palumbo, D. Pappalardo, and M. Gaibotti. 2006. Charge pump with adaptive stages for non-volatile memories. Proc. Circ., Devices Syst. 153, 2 (2006), 136--142.
[19]
Moinuddin K. Qureshi, Michele M. Franceschini, Ashish Jagmohan, and Luis A. Lastras. 2012. PreSET: Improving performance of phase change memories by exploiting asymmetry in write times. ACM SIGARCH Comput. Architect. News 40, 3 (2012), 380--391.
[20]
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. ACM SIGARCH Comput. Architect. News 37, 3 (2009), 24--33.
[21]
Luiz E. Ramos, Eugene Gorbatov, and Ricardo Bianchini. 2011. Page placement in hybrid memory systems. In Proceedings of the International Conference on Supercomputing (ISC’11). 85--95.
[22]
Wikipedia. 2016. Karnaugh map. Retrieved from https://en.wikipedia.org/wiki/Karnaugh_map.
[23]
Fei Xia, Dejun Jiang, Jin Xiong, Mingyu Chen, Lixin Zhang, and Ninghui Sun. 2014. DWC: Dynamic write consolidation for phase change memory systems. In Proceedings of the 28th ACM International Conference on Supercomputing (ICS’14). 211--220.
[24]
Byung-Do Yang, Jae-Eun Lee, Jang-Su Kim, Junghyun Cho, Seung-Yun Lee, and Byoung-Gon Yu. 2007. A low power phase-change random access memory using a data-comparison write scheme. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCA’07). 3014--3017.
[25]
Jianhui Yue and Yifeng Zhu. 2013. Accelerating write by exploiting PCM asymmetries. In Proceedings of the IEEE 19th International Symposium on High Performance Computer Architecture (HPCA’13). 282--293.
[26]
Deshan Zhang, Lei Ju, Mengying Zhao, Xiang Gao, and Zhiping Jia. 2016. Write-back aware shared last-level cache management for hybrid main memory. In Proceedings of the 53rd Design Automation Conference (DAC’16). 1--6.
[27]
Mengying Zhao, Yuan Xue, Chengmo Yang, and Chun Jason Xue. 2015. Minimizing MLC PCM write energy for free through profiling-based state remapping. In Proceedings of the 20th Asia and South Pacific Design Automation Conference (ASP-DAC’15). 502--507.

Cited By

View all
  • (2024)Efficient Audio Steganography Using Generalized Audio Intrinsic Energy With Micro-Amplitude Modification SuppressionIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.341726819(6559-6572)Online publication date: 1-Jan-2024
  • (2024)Provably Secure Public-Key Steganography Based on Elliptic Curve CryptographyIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.336121919(3148-3163)Online publication date: 1-Jan-2024
  • (2024)WIRE: Write Energy Reduction via Encoding in Phase Change Main Memories (PCM)Proceedings of the Future Technologies Conference (FTC) 2024, Volume 310.1007/978-3-031-73125-9_38(599-615)Online publication date: 8-Nov-2024
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Storage
ACM Transactions on Storage  Volume 14, Issue 3
Special Issue on FAST 2018 and Regular Papers
August 2018
210 pages
ISSN:1553-3077
EISSN:1553-3093
DOI:10.1145/3282875
  • Editor:
  • Sam H. Noh
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 November 2018
Accepted: 01 March 2018
Revised: 01 October 2017
Received: 01 January 2017
Published in TOS Volume 14, Issue 3

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. Phase change memory (PCM)
  2. charge pump
  3. pumping efficiency
  4. write regrouping

Qualifiers

  • Research-article
  • Research
  • Refereed

Funding Sources

  • US NSF
  • NJIT Research Startup Funds
  • NSFC

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)57
  • Downloads (Last 6 weeks)7
Reflects downloads up to 16 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2024)Efficient Audio Steganography Using Generalized Audio Intrinsic Energy With Micro-Amplitude Modification SuppressionIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.341726819(6559-6572)Online publication date: 1-Jan-2024
  • (2024)Provably Secure Public-Key Steganography Based on Elliptic Curve CryptographyIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.336121919(3148-3163)Online publication date: 1-Jan-2024
  • (2024)WIRE: Write Energy Reduction via Encoding in Phase Change Main Memories (PCM)Proceedings of the Future Technologies Conference (FTC) 2024, Volume 310.1007/978-3-031-73125-9_38(599-615)Online publication date: 8-Nov-2024
  • (2022)CORUSCANT: Fast Efficient Processing-in-Racetrack MemoriesProceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO56248.2022.00060(784-798)Online publication date: 1-Oct-2022
  • (2021)Forensics Through Stega Glasses: The Case of Adversarial ImagesPattern Recognition. ICPR International Workshops and Challenges10.1007/978-3-030-68780-9_37(453-469)Online publication date: 10-Jan-2021
  • (2020)Audio Steganography Based on Iterative Adversarial Attacks Against Convolutional Neural NetworksIEEE Transactions on Information Forensics and Security10.1109/TIFS.2019.296376415(2282-2294)Online publication date: 7-Feb-2020

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Full Access

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media