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Verification of coarse-grained reconfigurable arrays through random test programs

Published: 19 June 2018 Publication History

Abstract

We propose and evaluate a framework to test the functional correctness of coarse-grained reconfigurable array (CGRA) processors for pre-silicon verification and post-silicon validation. To reflect the reconfigurable nature of CGRAs, an architectural model of the system under test is built directly from the hardware description files. A guided place-and-routing algorithm is used to map operations and operands onto the heterogeneous processing elements (PE). Test coverage is maximized by favoring unexercised parts of the architecture. Requiring no explicit knowledge about the semantics of operations, the random test program generator (RTPG) framework seamlessly supports custom ISA extensions.
The proposed framework is applied to the Samsung Reconfigurable Processor, a modulo-scheduled CGRA integrated in smartphones, cameras, printers, and smart TVs. Experiments demonstrate that the RTPG is versatile, efficient, and quickly achieves a high coverage. In addition to detecting all randomly inserted faults, the generated test programs also exposed two yet unknown actual faults in the architecture.

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  • (2019)READYACM Transactions on Embedded Computing Systems10.1145/335818718:5s(1-20)Online publication date: 7-Oct-2019
  • (2019)Random test program generation for verification and validation of the Samsung Reconfigurable ProcessorJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2019.05.00797:C(219-238)Online publication date: 1-Aug-2019

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cover image ACM Conferences
LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems
June 2018
112 pages
ISBN:9781450358033
DOI:10.1145/3211332
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Badge change: Article originally badged under Version 1.0 guidelines https://www.acm.org/publications/policies/artifact-review-badging

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Published: 19 June 2018

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  1. Coarse-grained reconfigurable array
  2. random test program generation
  3. validation
  4. verification

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  • National Research Foundation of Korea

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LCTES '18

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Overall Acceptance Rate 116 of 438 submissions, 26%

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Cited By

View all
  • (2019)READYACM Transactions on Embedded Computing Systems10.1145/335818718:5s(1-20)Online publication date: 7-Oct-2019
  • (2019)Random test program generation for verification and validation of the Samsung Reconfigurable ProcessorJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2019.05.00797:C(219-238)Online publication date: 1-Aug-2019

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