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HASP '18: Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy
ACM2018 Proceeding
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
Conference:
HASP '18: Hardware and Architectural Support for Security and Privacy Los Angeles California 2 June 2018
ISBN:
978-1-4503-6500-0
Published:
02 June 2018
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Abstract

With recent, publicized security flaws in major computer processors, security and privacy research focusing on hardware and architecture has gained even more interest in the past year. In the era of cloud computing, smartphones and Internet of Things (IoT), industry and academia have to address the ever increasing challenges and requirements in order to meet the evolving landscape of security threats.

Over the years, the goal of HASP has been to bring together researchers, developers, and practitioners from academia and industry, to share new research results, practical insights, experiences and implementations related to all aspects of hardware and architectural support for security and privacy, and to discuss future trends in research and applications. We encourage contributions describing innovative work on hardware and architectural support for Internet of Things (IoT), smartphones and other smart devices, sensors and sensor networks, cloud computing and data centers which form the backbone of much of computing today.

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research-article
NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters
Article No.: 1, Pages 1–8https://doi.org/10.1145/3214292.3214293

This paper presents a novel run-time detection mechanism, called NIGHTs-WATCH, for access-driven cache-based Side-Channel Attacks (SCAs). It comprises of multiple machine learning models, which use real-time data from hardware performance counters for ...

research-article
Public Access
Cache timing side-channel vulnerability checking with computation tree logic
Article No.: 2, Pages 1–8https://doi.org/10.1145/3214292.3214294

Caches are one of the key features of modern processors as they help to improve memory access timing through caching recently used data. However, due to the timing differences between cache hits and misses, numerous timing side-channels have been ...

research-article
Public Access
BASTION-SGX: Bluetooth and Architectural Support for Trusted I/O on SGX
Article No.: 3, Pages 1–9https://doi.org/10.1145/3214292.3214295

This paper presents work towards realizing architectural support for Bluetooth Trusted I/O on SGX-enabled platforms, with the goal of providing I/O data protection that does not rely on system software security. Indeed, we are primarily concerned with ...

research-article
Public Access
An MLP-aware leakage-free memory controller
Article No.: 4, Pages 1–7https://doi.org/10.1145/3214292.3214296

Timing channels can be exploited to leak information between two virtual machines running on a shared server. Indeed, cache timing channels are important components in the Spectre attack. A shared memory controller can also be leveraged to establish a ...

research-article
Public Access
Spectres, virtual ghosts, and hardware support
Article No.: 5, Pages 1–9https://doi.org/10.1145/3214292.3214297

Side-channel attacks, such as Spectre and Meltdown, that leverage speculative execution pose a serious threat to computing systems. Worse yet, such attacks can be perpetrated by compromised operating system (OS) kernels to bypass defenses that protect ...

research-article
SMARTS: secure memory assurance of RISC-V trusted SoC
Article No.: 6, Pages 1–8https://doi.org/10.1145/3214292.3214298

Security is evolving fast as the prime design concern for modern System-on-Chip (SoC), especially for lightweight design choices. In this manuscript, we study the design of memory protection unit (MPU) that will be integrated in RISC-V trusted SoC, with ...

research-article
Rapid detection of rowhammer attacks using dynamic skewed hash tree
Article No.: 7, Pages 1–8https://doi.org/10.1145/3214292.3214299

RowHammer attacks pose a security threat to DRAM chips by causing bit-flips in sensitive memory regions. We propose a technique that combines a sliding window protocol and a dynamic integrity tree to rapidly detect multiple bit-flips caused by RowHammer ...

research-article
Position Paper: A case for exposing extra-architectural state in the ISA
Article No.: 8, Pages 1–6https://doi.org/10.1145/3214292.3214300

The recent Meltdown and Spectre attacks took the community by surprise. Rather than exploiting an incorrect implementation of the ISA, these attacks leverage the undocumented implementation-specific speculation behavior of high-performance ...

research-article
Public Access
A comparison study of intel SGX and AMD memory encryption technology
Article No.: 9, Pages 1–8https://doi.org/10.1145/3214292.3214301

Hardware-assisted trusted execution environments are secure isolation technologies that have been engineered to serve as efficient defense mechanisms to provide a security boundary at the system level. Hardware vendors have introduced a variety of ...

research-article
Public Access
Fault injection attacks on emerging non-volatile memory and countermeasures
Article No.: 10, Pages 1–8https://doi.org/10.1145/3214292.3214302

Emerging Non-Volatile Memories (NVMs) suffer from high and asymmetric read/write current and long write latency which can result in supply noise such as supply voltage droop and ground bounce. The magnitude of supply noise depends on the old data and ...

Contributors
  • Yale University
  • University of Houston
  • Princeton University

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Acceptance Rates

Overall Acceptance Rate 9 of 13 submissions, 69%
YearSubmittedAcceptedRate
HASP '1313969%
Overall13969%