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Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces

Published: 23 July 2018 Publication History

Abstract

In this paper, we propose a dynamic comparator that improved the operation performance of receiver (RX) with the effort to reduce power consumption. It is implemented via double-tail StrongARM latch comparator with an active inductor and efforts are made to minimize power consumption for high-speed resulting in better energy efficiency at the targeted high frequency. In this regard, our comparator is suitable for memory application RX to satisfy both low-power and high-speed. It is applied to the single-ended RX designed with a continuous-time linear equalizer, a clock generator and a quarter-rate 2-tap decision-feedback equalizer which is appropriate for the high-frequency memory application. Compared to the conventional one, our design, fabricated in 55nm CMOS process, provides an improvement of 7% in unit interval (UI) margin under the same power consumption and receives up to 10Gb/s PRBS15 data at BER < 10-12 with 0.4 UI margin and energy efficiency of 0.67pJ/bit.

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Cited By

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  • (2024)Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory InterfacesIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2024.348813573(1-8)Online publication date: 2024
  • (2023)Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM MeasurementIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2023.331868772(1-10)Online publication date: 2023

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cover image ACM Conferences
ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design
July 2018
327 pages
ISBN:9781450357043
DOI:10.1145/3218603
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 23 July 2018

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Author Tags

  1. Active Inductor
  2. Decision Feedback Equalizer
  3. Dynamic comparator
  4. StrongARM latch
  5. Timing Critical Path

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Cited By

View all
  • (2024)Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory InterfacesIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2024.348813573(1-8)Online publication date: 2024
  • (2023)Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM MeasurementIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2023.331868772(1-10)Online publication date: 2023

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