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Integrated Synthesis Methodology for Crossbar Arrays

Published: 17 July 2018 Publication History

Abstract

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.

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Cited By

View all
  • (2021)Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault ToleranceIEEE Transactions on Nanotechnology10.1109/TNANO.2020.304401720(39-53)Online publication date: 1-Jan-2021
  • (2021)Defect-Tolerant Mapping of CMOL Circuit Targeting Delay OptimizationJournal of Computer Science and Technology10.1007/s11390-021-0904-036:5(1118-1132)Online publication date: 30-Sep-2021
  • (2020)Nano-Crossbar based Computing: Lessons Learned and Future Directions2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116566(382-387)Online publication date: Mar-2020
  • Show More Cited By

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cover image ACM Conferences
NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures
July 2018
176 pages
ISBN:9781450358156
DOI:10.1145/3232195
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 17 July 2018

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Author Tags

  1. Crossbar Arrays
  2. Defect Tolerance
  3. Fault Tolerance
  4. Logic Synthesis
  5. Memristor Arrays
  6. Performance Optimization

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  • Research-article
  • Research
  • Refereed limited

Funding Sources

  • TUBITAK-Career
  • European Union?s H2020 - Research and Innovation Staff Exchange - Marie Sklodowska-Curie Action

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NANOARCH '18
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NANOARCH '18 Paper Acceptance Rate 30 of 56 submissions, 54%;
Overall Acceptance Rate 55 of 87 submissions, 63%

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Cited By

View all
  • (2021)Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault ToleranceIEEE Transactions on Nanotechnology10.1109/TNANO.2020.304401720(39-53)Online publication date: 1-Jan-2021
  • (2021)Defect-Tolerant Mapping of CMOL Circuit Targeting Delay OptimizationJournal of Computer Science and Technology10.1007/s11390-021-0904-036:5(1118-1132)Online publication date: 30-Sep-2021
  • (2020)Nano-Crossbar based Computing: Lessons Learned and Future Directions2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116566(382-387)Online publication date: Mar-2020
  • (2020)Stuck-At Fault Mitigation of Emerging Technologies Based Switching LatticesJournal of Electronic Testing10.1007/s10836-020-05885-2Online publication date: 2-Jun-2020
  • (2019)Analog Neural Network based on Memristor Crossbar Arrays2019 11th International Conference on Electrical and Electronics Engineering (ELECO)10.23919/ELECO47770.2019.8990597(358-361)Online publication date: Nov-2019
  • (2019)Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model2019 IEEE Latin American Test Symposium (LATS)10.1109/LATW.2019.8704615(1-6)Online publication date: Mar-2019
  • (2019)Noise-induced Performance Enhancement of Variability-aware Memristor Networks2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS46596.2019.8965134(731-734)Online publication date: Nov-2019

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