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Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices

Published: 17 July 2018 Publication History

Abstract

In this paper, we explore the possibility of hardware acceleration implementation of sparse coding algorithm with spintronic devices by a series of design optimizations across the architecture, circuit and device. Firstly, a domain wall motion (DWM) based compound spintronic device (CSD) is engineered and modelled, which is envisioned to achieve multiple conductance states. Sequentially, a parallel architecture is presented based on a dense cross-point array of the proposed DWM based CSD, where each dictionary (D) value can be mapped into the conductance of the proposed DWM based CSD at the corresponding cross-point. Benefitting from its massively parallel read and write operation, such proposed parallel architecture can accelerate the selected sparse coding algorithm using a designed dedicated periphery read and write circuit. Experimental results show that the selected sparse coding algorithm can be accelerated by 1400x with the proposed parallel architecture in comparison with software implementation. Moreover, its energy dissipation is 8 orders of magnitude smaller than that with software implementation.

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Cited By

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  • (2021)VG-SOT MRAM Design and Performance Analysis2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)10.1109/IEMCON53756.2021.9623147(0715-0719)Online publication date: 27-Oct-2021
  • (2019)Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)10.1109/NANOARCH47378.2019.181295(1-6)Online publication date: Jul-2019

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  1. Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices

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      cover image ACM Conferences
      NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures
      July 2018
      176 pages
      ISBN:9781450358156
      DOI:10.1145/3232195
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 17 July 2018

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      Author Tags

      1. ANN
      2. DWM
      3. MTJ
      4. Sparse coding
      5. hardware acceleration
      6. multiple conductance states
      7. neuromorphic computing

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      Funding Sources

      • National Science Foundation of China projects
      • International Collaboration Project 2015DFE12880 from the Ministry of Science and Technology in China
      • project from Beijing Municipal of Science and Technology

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      NANOARCH '18 Paper Acceptance Rate 30 of 56 submissions, 54%;
      Overall Acceptance Rate 55 of 87 submissions, 63%

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      Cited By

      View all
      • (2021)VG-SOT MRAM Design and Performance Analysis2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)10.1109/IEMCON53756.2021.9623147(0715-0719)Online publication date: 27-Oct-2021
      • (2019)Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)10.1109/NANOARCH47378.2019.181295(1-6)Online publication date: Jul-2019

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