research-article

A ferroelectric FET based power-efficient architecture for data-intensive computing

Authors:

Prakshi Rastogi,

Asif Islam Khan,

Sudhakar Yalamanchili,

Saibal MukhopadhyayAuthors Info & Claims

ICCAD '18: Proceedings of the International Conference on Computer-Aided Design

Article No.: 32, Pages 1 - 8

https://doi.org/10.1145/3240765.3240770

Published: 05 November 2018 Publication History

Abstract

In this paper, we present a ferroelectric FET (FeFET) based power-efficient architecture to accelerate data-intensive applications such as deep neural networks (DNNs). We propose a cross-cutting solution combining emerging device technologies, circuit optimizations, and micro-architecture innovations. At device level, FeFET crossbar is utilized to perform vector-matrix multiplication (VMM). As a field effect device, FeFET significantly reduces the read/write energy compared with the resistive random-access memory (ReRAM). At circuit level, we propose an all-digital peripheral design, reducing the large overhead introduced by ADC and DAC in prior works. In terms of micro-architecture innovation, a dedicated hierarchical network-on-chip (H-NoC) is developed for input broadcasting and on-the-fly partial results processing, reducing the data transmission volume and latency. Speed, power, area and computing accuracy are evaluated based on detailed device characterization and system modeling. For DNN computing, our design achieves 254x and 9.7x gain in power efficiency (GOPS/W) compared to GPU and ReRAM based designs, respectively.

References

[1]

P. Chi et al., "PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory," in ACM SIGARCH Computer Architecture News, 2016, vol. 44, no. 3, pp. 27--39: IEEE Press.

Digital Library

[2]

A. Shafiee et al., "ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars," ACM SIGARCH Computer Architecture News, vol. 44, no. 3, pp. 14--26, 2016.

Digital Library

[3]

L. Song, X. Qian, H. Li, and Y. Chen, "PipeLayer: A pipelined ReRAM-based accelerator for deep learning," in High Performance Computer Architecture (HPCA), 2017 IEEE International Symposium on, 2017, pp. 541--552: IEEE.

[4]

D. Fujiki, S. Mahlke, and R. Das, "In-Memory Data Parallel Processor," in Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018, pp. 1--14: ACM.

Digital Library

[5]

S. Yu, B. Gao, Z. Fang, H. Yu, J. Kang, and H.-S. P. Wong, "A neuromorphic visual system using RRAM synaptic devices with sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling," in Electron Devices Meeting (IEDM), 2012 IEEE International, 2012, pp. 10.4. 1--10.4. 4: IEEE.

[6]

S. Yu et al., "Binary neural network with 16 Mb RRAM macro chip for classification and online training," in Electron Devices Meeting (IEDM), 2016 IEEE International, 2016, pp. 16.2. 1--16.2. 4: IEEE.

[7]

C. Nail et al., "Understanding RRAM endurance, retention and window margin trade-off using experimental results and simulations," in Electron Devices Meeting (IEDM), 2016 IEEE International, 2016, pp. 4.5. 1--4.5. 4: IEEE.

[8]

S. Park et al., "Neuromorphic speech systems using advanced ReRAM-based synapse," in Electron Devices Meeting (IEDM), 2013 IEEE International, 2013, pp. 25.6. 1--25.6. 4: IEEE.

[9]

M. Trentzsch et al., "A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs," in Electron Devices Meeting (IEDM), 2016 IEEE International, 2016, pp. 11.5. 1--11.5. 4: IEEE.

[10]

J. Muller, T. S. Boscke, U. Schroder, R. Hoffmann, T. Mikolajick, and L. Frey, "Nanosecond Polarization Switching and Long Retention in a Novel MFIS-FET Based on Ferroelectric $\hbox {HfO} _ {2} $," IEEE Electron Device Letters, vol. 33, no. 2, pp. 185--187, 2012.

[11]

M. Lee et al., "Physical thickness 1. x nm ferroelectric HfZrOx negative capacitance FETs," in Electron Devices Meeting (IEDM), 2016 IEEE International, 2016, pp. 12.1. 1--12.1. 4: IEEE.

[12]

H. Mulaosmanovic et al., "Novel ferroelectric FET based synapse for neuromorphic systems," in VLSI Technology, 2017 Symposium on, 2017, pp. T176--T177: IEEE.

[13]

A. Aziz, "Computing with Ferroelectric FETs: Devices, Models, Systems, and Applications," presented at the DATE, 2018.

[14]

X. Y. Xiaoming Chen, Michael Niemier, Xiaobo Sharon Hu, "Design and Optimization of FeFET-based Crossbars for Binary Convolution Neural Networks," presented at the DATE, 2018.

[15]

Y. Chen et al., "Dadiannao: A machine-learning supercomputer," in Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, pp. 609--622: IEEE Computer Society.

Digital Library

[16]

N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, "CACTI 6.0: A tool to model large caches," HP laboratories, pp. 22--31, 2009.

[17]

H. M. C. Consortium, "Hybrid memory cube specification 1.0," Last Revision Jan, 2013.

[18]

B. Gao et al., "Ultra-low-energy three-dimensional oxide-based electronic synapses for implementation of robust high-accuracy neuromorphic computation systems," ACS nano, vol. 8, no. 7, pp. 6998--7004, 2014.

[19]

S. Han et al., "Ese: Efficient speech recognition engine with sparse lstm on fpga," in Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017, pp. 75--84: ACM.

Digital Library

Cited By

Han LHuang PZhou ZChen YLiu XKang J(2023)A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247977(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247977
Luo YWang PYu S(2022)Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision SynapseACM Journal on Emerging Technologies in Computing Systems10.1145/347346118:2(1-20)Online publication date: 12-Jan-2022
https://dl.acm.org/doi/10.1145/3473461
Rafiq MParihar SChauhan YSahay S(2022)Efficient Implementation of Max-Pooling Algorithm Exploiting History-Effect in Ferroelectric-FinFETsIEEE Transactions on Electron Devices10.1109/TED.2022.320711469:11(6446-6452)Online publication date: Nov-2022
https://doi.org/10.1109/TED.2022.3207114
Show More Cited By

Recommendations

Ferroelectric FET Based In-Memory Computing for Few-Shot Learning
GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

As CMOS technology advances, the performance gap between the CPU and main memory has not improved. Furthermore, the hardware deployed for Internet of Things (IoT) applications need to process ever growing volumes of data, which can further exacerbate the ...
Nonvolatile memory design based on ferroelectric FETs
DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of low power nonvolatile memories by virtue of their three-terminal structure coupled with the ability of the ferroelectric (FE) material to retain its polarization in the absence ...
Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Content Addressable Memory (CAM) is widely used for associative search tasks in advanced machine learning models and data-intensive applications due to the highly parallel pattern matching capability. Most state-of-the-art CAM designs focus on reducing ...

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences

ICCAD '18: Proceedings of the International Conference on Computer-Aided Design

November 2018

1020 pages

ISBN:9781450359504

DOI:10.1145/3240765

General Chair:
Iris Bahar
Brown Univ. School of Engineering, Providence, RI

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

IEEE-EDS: Electronic Devices Society
IEEE CAS
IEEE CEDA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2018

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Conference

ICCAD '18

Sponsor:

IEEE-EDS

ICCAD '18: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN

November 5 - 8, 2018

California, San Diego

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

17
Total Citations
View Citations
885
Total Downloads

Downloads (Last 12 months)123
Downloads (Last 6 weeks)6

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Han LHuang PZhou ZChen YLiu XKang J(2023)A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247977(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247977
Luo YWang PYu S(2022)Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision SynapseACM Journal on Emerging Technologies in Computing Systems10.1145/347346118:2(1-20)Online publication date: 12-Jan-2022
https://dl.acm.org/doi/10.1145/3473461
Rafiq MParihar SChauhan YSahay S(2022)Efficient Implementation of Max-Pooling Algorithm Exploiting History-Effect in Ferroelectric-FinFETsIEEE Transactions on Electron Devices10.1109/TED.2022.320711469:11(6446-6452)Online publication date: Nov-2022
https://doi.org/10.1109/TED.2022.3207114
Dash SLuo YLu AYu SMukhopadhyay S(2022)Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision ComputationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307840841:4(1006-1019)Online publication date: Apr-2022
https://doi.org/10.1109/TCAD.2021.3078408
Yayla MBuschjager SGupta AChen JHenkel JMorik KChen KAmrouch H(2022)FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit ErrorsIEEE Transactions on Computers10.1109/TC.2021.310473671:7(1681-1695)Online publication date: 1-Jul-2022
https://doi.org/10.1109/TC.2021.3104736
Luo YDutta SKaul ALim SBakir MDatta SYu S(2022)A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable InterconnectIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2022.317757712:2(445-457)Online publication date: Jun-2022
https://doi.org/10.1109/JETCAS.2022.3177577
Lu XChen SPang ZSun SYin XZhuo C(2022)In-Memory Multi-Bit Multiplication and Accumulation (MAC) Using FeFET for Energy Efficient IoT2022 2nd International Conference on Intelligent Technology and Embedded Systems (ICITES)10.1109/ICITES56274.2022.9943617(27-33)Online publication date: 23-Sep-2022
https://doi.org/10.1109/ICITES56274.2022.9943617
Lee MShe XChakraborty BDash SMudassar BMukhopadhyay S(2021)Reliable Edge Intelligence in Unreliable Environment2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474097(896-901)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474097
Luo YYu S(2021)AILC: Accelerate On-Chip Incremental Learning With Compute-in-Memory TechnologyIEEE Transactions on Computers10.1109/TC.2021.305319970:8(1225-1238)Online publication date: 1-Aug-2021
https://doi.org/10.1109/TC.2021.3053199
Kang BLu ALong YKim DYu SMukhopadhyay S(2021)Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory ArchitectureIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2021.312712911:4(649-662)Online publication date: Dec-2021
https://doi.org/10.1109/JETCAS.2021.3127129
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten