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DALS: Delay-driven Approximate Logic Synthesis

Published: 05 November 2018 Publication History

Abstract

Approximate computing is an emerging paradigm for error-tolerant applications. By introducing a reasonable amount of inaccuracy, both the area and delay of a circuit can be reduced significantly. To synthesize approximate circuits automatically, many approximate logic synthesis (ALS) algorithms have been proposed. However, they mainly focus on area reduction and are not optimal in reducing the delay of the circuits. In this paper, we propose DALS, a delay-driven ALS framework. DALS works on the AND-inverter graph (AIG) representation of a circuit. It supports a wide range of approximate local changes and some commonly-used error metrics, including error rate and mean error distance. In order to select an optimal set of nodes in the AIG to apply approximate local changes, DALS establishes a critical error network (CEN) from the AIG and formulates a maximum flow problem on the CEN. Our experimental results on a wide range of benchmarks show that DALS produces approximate circuits with significantly reduced delays.

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Cited By

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  • (2023)HEDALS: Highly Efficient Delay-Driven Approximate Logic SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326822142:11(3491-3504)Online publication date: Nov-2023
  • (2023)AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247856(1-6)Online publication date: 9-Jul-2023
  • (2022)VECBEE: A Versatile Efficiency–Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314971741:11(5085-5099)Online publication date: Nov-2022
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          cover image Guide Proceedings
          2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
          Nov 2018
          939 pages

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          IEEE Press

          Publication History

          Published: 05 November 2018

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          View all
          • (2023)HEDALS: Highly Efficient Delay-Driven Approximate Logic SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326822142:11(3491-3504)Online publication date: Nov-2023
          • (2023)AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247856(1-6)Online publication date: 9-Jul-2023
          • (2022)VECBEE: A Versatile Efficiency–Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314971741:11(5085-5099)Online publication date: Nov-2022
          • (2022)Quantified Satisfiability-based Simultaneous Selection of Multiple Local Approximate Changes under Maximum Error Bound2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937529(3498-3502)Online publication date: 28-May-2022
          • (2022)Probability-Based DSE of Approximated LUT-Based FPGA Designs2022 IEEE 15th Dallas Circuit And System Conference (DCAS)10.1109/DCAS53974.2022.9845591(1-5)Online publication date: 17-Jun-2022
          • (2021)Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401451(1-5)Online publication date: May-2021
          • (2020)Probabilistic error propagation through approximated boolean networksProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437727(1-6)Online publication date: 20-Jul-2020

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