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Design and Algorithm for Clock Gating and Flip-flop Co-optimization

Published: 05 November 2018 Publication History

Abstract

This work firstly investigates the problem of how designing data-driven (i.e., toggling based) clock gating can be closely integrated with the synthesis of flip-flops, which has never been addressed in the prior clock gating works. Our key observation is that some internal part of a flip-flop cell can be reused to generate its clock gating enable signal. Based on this, we propose a newly optimized flip-flop wiring structure, called eXOR-FF, in which an internal logic can be reused for every clock cycle to decide if the flip-flop is to be activated or inactivated through clock gating, thereby achieving area saving (thus, leakage as well as dynamic power saving) on every pair of flip-flop and its toggling detection logic. Then, we propose a comprehensive methodology of placement/timing-aware clock gating exploration that provides two unique strengths: best suited for maximally exploiting the benefit of eXOR-FFs and precise analyses on the decomposition of power consumptions and timing impact, and translating them into cost functions in core engine of clock gating exploration.

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Cited By

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  • (2023)Maximizing Power Saving Through State-Driven Clock Gating2023 20th International SoC Design Conference (ISOCC)10.1109/ISOCC59558.2023.10396230(123-124)Online publication date: 25-Oct-2023
  • (2023)Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181800(1-5)Online publication date: 21-May-2023
  • (2022)On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategiesInternational Journal of Electronics10.1080/00207217.2022.2158493111:1(184-203)Online publication date: 28-Dec-2022
  • Show More Cited By

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          cover image Guide Proceedings
          2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
          Nov 2018
          939 pages

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          IEEE Press

          Publication History

          Published: 05 November 2018

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          View all
          • (2023)Maximizing Power Saving Through State-Driven Clock Gating2023 20th International SoC Design Conference (ISOCC)10.1109/ISOCC59558.2023.10396230(123-124)Online publication date: 25-Oct-2023
          • (2023)Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181800(1-5)Online publication date: 21-May-2023
          • (2022)On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategiesInternational Journal of Electronics10.1080/00207217.2022.2158493111:1(184-203)Online publication date: 28-Dec-2022
          • (2021)Integrated Clock Gating Analysis of TG Based D Flip-Flop for Different Technology NodesRecent Trends in Electronics and Communication10.1007/978-981-16-2761-3_9(97-106)Online publication date: 14-Dec-2021
          • (2020)Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)10.1109/UPCON50219.2020.9376565(1-6)Online publication date: 27-Nov-2020

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