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Design automation methodology and tools for superconductive electronics

Published: 05 November 2018 Publication History

Abstract

Josephson junction-based superconducting logic families have been proposed to implement analog and digital signals, which can achieve low energy dissipation and ultra-fast switching speed. There are two representative technologies: DC-biased RSFQ (rapid single flux quantum) technology and its variants that achieve a verified speed of 370 Ghz, and AC-biased AQFP (adiabatic quantum-flux-parametron) that achieves an energy dissipation near quantum limits. Despite extraordinary characteristics of the superconducting logic families, many technical challenges remain, including the choice of circuit fabrics and architectures that utilize the SFQ technology and the development of effective design automation methodologies and tools. This paper presents our work on developing design flows and tools for DC- and AC-biased SFQ circuits, leveraging unique characteristics and design requirements of the SFQ logic families. More precisely, physical design algorithms, including placement, clock tree routing, and signal routing algorithms targeting RSFQ circuits are presented first. Next, a majority/minority gate-based automatic synthesis framework targeting AQFP logic circuits is described. Finally, experimental results to demonstrate the efficacy of the proposed framework and tools are presented.

References

[1]
{n. d.}. TOP500 Supercomputer Sites. ({n. d.}). https://www.top500.org/ https://www.top500.org/.
[2]
{n. d.}. âĂIJOpen Circuit Design,âĂİ Aug. 2016. ({n. d.}). {Online}.Available:http://opencircuitdesign.com/qrouter/index.html
[3]
Robert Brayton and Alan Mishchenko. 2010. ABC: An Academic Industrial-strength Verification Tool. In Proceedings of the 22Nd International Conference on Computer Aided Verification (CAV'10). Springer-Verlag, Berlin, Heidelberg, 24--40.
[4]
Paul Bunyk, Konstantin Likharev, and Dmitry Zinoviev. 2001. RSFQ technology: Physics and devices. International journal of high speed electronics and systems 11, 01 (2001), 257--305.
[5]
PI Bunyk, A Oliva, VK Semenov, M Bhushan, KK Likharev, JE Lukens, MB Ketchen, and WH Mallison. 1995. High-speed single-flux-quantum circuit using planarized niobium-trilayer Josephson junction technology. Applied physics letters 66, 5 (1995), 646--648.
[6]
John Clarke and Alex I. Braginski. 2004. The SQUID Handbook: Fundamentals and Technology of SQUIDs and SQUID Systems (1 ed.). Wiley-VCH.
[7]
Quentin P Herr, Anna Y Herr, Oliver T Oberg, and Alexander G Ioannidis. 2011. Ultra-low-power superconductor logic. Journal of applied physics 109, 10 (2011), 103903.
[8]
George Karypis and Vipin Kumar. 2000. Multilevel k-way hypergraph partitioning. VLSI design 11, 3 (2000), 285--300.
[9]
Naveen Katam and Massoud Pedram. 2018. Logic Optimization, Complex Cell Design and Retiming of Single Flux Quantum Circuits. IEEE Trans. on Applied Superconductivity (2018).
[10]
Myung-Chul Kim, Dong-Jin Lee, and Igor L Markov. 2012. SimPL: An effective placement algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 1 (2012), 50--60.
[11]
D. E. Kirichenko, S. Sarwana, and A. F. Kirichenko. 2011. Zero Static Power Dissipation Biasing of RSFQ Circuits. IEEE Transactions on Applied Superconductivity 21, 3 (June 2011), 776--779.
[12]
Kun Kong, Yun Shang, and Ruqian Lu. 2010. An optimized majority logic synthesis methodology for quantum-dot cellular automata. IEEE Transactions on Nanotechnology 9, 2 (2010), 170--183.
[13]
Charles Leiserson and James Saxe. 1991. Retiming Synchronous Circuitry. Algorithmica (1991).
[14]
Konstantin K Likharev and Vasilii K Semenov. 1991. RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock-frequency digital systems. IEEE Transactions on Applied Superconductivity 1, 1 (1991), 3--28.
[15]
Ghasem Pasandi and Massoud Pedram. 2018. RSFQmap: A Novel Technology Mapping Tool for Rapid Single Flux Quantum (RSFQ) Electronics. Proc. of ISCAS (2018).
[16]
Soheil Nazar Shahsavani, Ting-Ru Lin, Alireza Shafaei, Coenrad J Fourie, and Massoud Pedram. 2017. An integrated row-based cell placement and interconnect synthesis tool for large SFQ logic circuits. IEEE Transactions on Applied Superconductivity 27, 4 (2017), 1--8.
[17]
Soheil Nazar Shahsavani, Alireza Shafaei, and Massoud Pedram. 2018. A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018. IEEE, 1465--1468.
[18]
Arman Shehabi, Sarah Josephine Smith, Dale A. Sartor, Richard E. Brown, Magnus Herrlin, Jonathan G. Koomey, Eric R. Masanet, Horner Nathaniel, InÃČÂłs Lima Azevedo, Lintner, and William. 2016. United States Data Center Energy Usage Report. Technical Report LBNL-1005775. Lawrence Berkeley National Laboratory. https://eta.lbl.gov/publications/org
[19]
Peter Spindler, Ulf Schlichtmann, and Frank M Johannes. 2008. Kraftwerk2 - A fast force-directed quadratic placement approach using an accurate net model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, 8 (2008), 1398--1411.
[20]
Naoki Takeuchi, Dan Ozawa, Yuki Yamanashi, and Nobuyuki Yoshikawa. 2013. An adiabatic quantum flux parametron as an ultra-low-power logic device. Superconductor Science and Technology 26, 3 (2013), 035010.
[21]
Naoki Takeuchi, Yuki Yamanashi, and Nobuyuki Yoshikawa. 2015. Adiabatic quantum-flux-parametron cell library adopting minimalist design. Journal of Applied Physics 117, 17 (5 2015), 173912.
[22]
Sergey K Tolpygo, Vladimir Bolkhovsky, Terence J Weir, Leonard M Johnson, Mark A Gouker, and William D Oliver. 2015. Fabrication process and properties of fully-planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits. IEEE Trans. Appl. Supercond 25, 3 (2015), 1101312.
[23]
Clifford Wolf. 2016. Yosys open synthesis suite. (2016).
[24]
Nobuyuki Yoshikawa and Y Kato. 1999. Reduction of power consumption of RSFQ circuits by inductance-load biasing. Superconductor Science and Technology 12, 11 (1999), 918.

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  • (2024)A Combinational Logic Optimization Method for Large-Scale SFQ CircuitsIEEE Transactions on Applied Superconductivity10.1109/TASC.2024.345431434:9(1-8)Online publication date: Dec-2024
  • (2024)Preventing short violations in clock routing with an SVM classifier before powerplanning and placementMicroelectronics Journal10.1016/j.mejo.2024.106429153(106429)Online publication date: Nov-2024
  • (2023)EDA for Superconductive ElectronicsSingle Flux Quantum Integrated Circuit Design10.1007/978-3-031-47475-0_14(179-198)Online publication date: 17-Nov-2023
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Published In

cover image ACM Other conferences
ICCAD '18: Proceedings of the International Conference on Computer-Aided Design
November 2018
1020 pages
ISBN:9781450359504
DOI:10.1145/3240765
  • General Chair:
  • Iris Bahar
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • IEEE-EDS: Electronic Devices Society
  • IEEE CAS
  • IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2018

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Author Tags

  1. design automation
  2. single flux quantum logic
  3. superconductive electronics

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ICCAD '18
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  • IEEE-EDS

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all
  • (2024)A Combinational Logic Optimization Method for Large-Scale SFQ CircuitsIEEE Transactions on Applied Superconductivity10.1109/TASC.2024.345431434:9(1-8)Online publication date: Dec-2024
  • (2024)Preventing short violations in clock routing with an SVM classifier before powerplanning and placementMicroelectronics Journal10.1016/j.mejo.2024.106429153(106429)Online publication date: Nov-2024
  • (2023)EDA for Superconductive ElectronicsSingle Flux Quantum Integrated Circuit Design10.1007/978-3-031-47475-0_14(179-198)Online publication date: 17-Nov-2023
  • (2022)Surface Inductance of Superconductive StriplinesIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2022.315653369:6(2952-2956)Online publication date: Jun-2022
  • (2022)Superconducting single flux quantum (SFQ) technology for power-efficiency computingCCF Transactions on High Performance Computing10.1007/s42514-022-00114-y4:2(182-210)Online publication date: 21-Jul-2022
  • (2021)Design Automation of Superconductive Digital Circuits: A reviewIEEE Nanotechnology Magazine10.1109/MNANO.2021.311321815:6(54-67)Online publication date: Dec-2021
  • (2021)EDA for Superconductive ElectronicsSingle Flux Quantum Integrated Circuit Design10.1007/978-3-030-76885-0_7(95-114)Online publication date: 29-May-2021
  • (2020)A Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLsIEEE Transactions on Applied Superconductivity10.1109/TASC.2020.301492830:7(1-6)Online publication date: Oct-2020
  • (2020)SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00018(58-72)Online publication date: Oct-2020
  • (2019)A Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic CircuitsIEEE Transactions on Applied Superconductivity10.1109/TASC.2019.2943930(1-1)Online publication date: 2019
  • Show More Cited By

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