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Estimating and Optimizing BTl Aging Effects: From Physics to CAD

Published: 05 November 2018 Publication History

Abstract

Transistor aging due to Bias Temperature Instability (BTI) is a crucial degradation that affects the reliability of circuits over time. Aging-aware circuit design flows do virtually not exist yet and even research is in its infancy. In this work, we demonstrate how the deleterious effects BTI-induced degradations can be modeled from physics, where they do occur, all the way up to the system level, where they finally take place and affect the delay and power of circuits. To achieve that, degradation-aware cell libraries, that properly capture the impact of BTI not only on the delay of standard cells but also on their static and dynamic power, are created. Unlike state of the art, which solely models the impact of BTI on the threshold voltage of transistors <tex>$(V_{th})$</tex>, we are the first to model the other key transistor parameters degraded by BTI like carrier mobility (<tex>$\mu$</tex>), sub-threshold slope (<tex>$SS$</tex>), and gate-drain capacitance <tex>$(C_{gd})$</tex>. Our cell libraries are compatible with existing commercial CAD tools. Employing the mature algorithms in such tools, enables designers &#x2013; after importing our cell libraries &#x2013; to accurately estimate the overall impact of aging on changing the delay and/or power of any circuit, despite its complexity. We demonstrate that <tex>$\Delta V_{th}$</tex> alone (as done in state of the art) is insufficient to correctly model the impact of BTI either on delay or power of circuits. On the one hand, neglecting BTl-induced <tex>$\mu$</tex> and <tex>$C_{gd}$</tex> degradations leads to underestimating the impact that BTI has on increasing the delay of circuits. Hence, designers will employ narrower timing guardbands in which reliability of circuits during lifetime cannot be sustained. On the other hand, neglecting BTI-induced <tex>$SS$</tex> degradation leads to overestimating the impact that BTI has on static power reduction. Hence, the potential benefit of circuits from BTI will be exaggerated.

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Cited By

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  • (2020)Exploiting Configurable Approximations for Tolerating Aging-induced Timing ViolationsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2019KEP0009E103.A:9(1028-1036)Online publication date: 1-Sep-2020
  • (2019)Tolerating Aging-Induced Timing Violations Via Configurable Approximations2019 IEEE 8th Global Conference on Consumer Electronics (GCCE)10.1109/GCCE46687.2019.9015592(1023-1026)Online publication date: Oct-2019
  • (2018)PVT2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/3240765.3243491(1-6)Online publication date: 5-Nov-2018
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        2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
        Nov 2018
        939 pages

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        Published: 05 November 2018

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        • (2020)Exploiting Configurable Approximations for Tolerating Aging-induced Timing ViolationsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2019KEP0009E103.A:9(1028-1036)Online publication date: 1-Sep-2020
        • (2019)Tolerating Aging-Induced Timing Violations Via Configurable Approximations2019 IEEE 8th Global Conference on Consumer Electronics (GCCE)10.1109/GCCE46687.2019.9015592(1023-1026)Online publication date: Oct-2019
        • (2018)PVT2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/3240765.3243491(1-6)Online publication date: 5-Nov-2018
        • (2018)Performance and Accuracy in Soft-Error Resilience Evaluation using the Multi-Level Processor Simulator ETISS-ML2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/3240765.3243490(1-8)Online publication date: 5-Nov-2018
        • (2018)Multi-Physics-based FEM Analysis for Post-voiding Analysis of Electromigration Failure Effects2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/3240765.3243486(1-8)Online publication date: 5-Nov-2018

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