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Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems

Published: 08 February 2019 Publication History

Abstract

Rapid progress in technology scaling has introduced massive parallel computing systems with multiple cores on the integrated circuit (IC), in which a flexible and scalable packet-switched architecture, Network-on-Chip (NoC), is commonly used for communication among the cores. However, technology scaling has also increased the susceptibility to internal defects in such systems. So, manufacturing tests of such multicore systems is crucial and this is a complex and time-consuming process. Due to stress on time-to-market, test engineers focus on the reduction of testtime and perform parallel tests of cores. Due to aggressive technology scaling into the nanometer regime, power consumption is also becoming a significant burden. Moreover, power consumption during manufacturing tests is more as compared to normal operation. In addition, peak power consumption is often significantly higher than the average power values. The consumed power leads to high temperature and creates hotspots, which in turn leads to failure of good parts, resulting in yield loss. Thermal safety during testing is an utmost challenging problem in NoC-based multicore systems, including three-dimensional NoC-based (3D NoC) multicore systems due to stacking of layers. This work proposes a preemptive test scheduling technique for NoC-based multicore systems to reduce the testtime by minimizing conflicts of resource usage. The preemptive test scheduling problem has been formulated using Integer Linear Programming (ILP). In this article, authors have also presented a thermal-aware test scheduling technique to test cores in 2D as well as 3D stacked NoC-based multicore systems using a Particle Swarm Optimization (PSO) based approach. To improve the solution further, several innovative augmentation techniques have been incorporated in the basic PSO. Experimental results highlight the effectiveness of the proposed method in reducing testtime and peak temperature under the power constraints and achieve a tradeoff between testtime and peak temperature.

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  • (2024)Thermal-aware application mapping using genetic and fuzzy logic techniques for minimizing temperature in three-dimensional network-on-chipThe Journal of Supercomputing10.1007/s11227-023-05869-x80:8(11214-11240)Online publication date: 1-May-2024
  • (2023)Detection and Localization of Channel-Short Faults in Regular On-Chip Interconnection NetworksSN Computer Science10.1007/s42979-023-02102-74:5Online publication date: 30-Aug-2023
  • (2021)Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.305966229:5(1009-1021)Online publication date: 1-May-2021
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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems  Volume 15, Issue 1
Special Issue on Emerging Networks-on-Chip and Regular Papers
January 2019
283 pages
ISSN:1550-4832
EISSN:1550-4840
DOI:10.1145/3303864
  • Editor:
  • Yuan Xie
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 08 February 2019
Accepted: 01 July 2018
Revised: 01 May 2018
Received: 01 December 2017
Published in JETC Volume 15, Issue 1

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Author Tags

  1. 3D NoC
  2. Network-on-chip (NoC)
  3. TSV placement
  4. application mapping

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View all
  • (2024)Thermal-aware application mapping using genetic and fuzzy logic techniques for minimizing temperature in three-dimensional network-on-chipThe Journal of Supercomputing10.1007/s11227-023-05869-x80:8(11214-11240)Online publication date: 1-May-2024
  • (2023)Detection and Localization of Channel-Short Faults in Regular On-Chip Interconnection NetworksSN Computer Science10.1007/s42979-023-02102-74:5Online publication date: 30-Aug-2023
  • (2021)Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.305966229:5(1009-1021)Online publication date: 1-May-2021
  • (2020)Multi-station test scheduling optimization method for industrial robot servo systemJournal of Ambient Intelligence and Humanized Computing10.1007/s12652-020-02577-9Online publication date: 15-Oct-2020

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