Kenji Kise
ABSTRACT
A hardware module called merge network is the key module for constructing FPGA-based sorting accelerators. Therefore, we propose a novel merge network based on compare and swap operations for high performance sorting accelerators. Our proposal is based on the state-of-the-art merge network and it tries to mitigate its drawback that the maximum wiring delay and the maximum fanout increase when the number of records output per cycle is increased.
We implement some merge networks adopting the proposal on a Virtex-7 FPGA. The evaluation results show that the maximum fanout of the proposal is constant, and the maximum wiring delay of the proposal is almost constant. Because of these desirable properties, the proposal of the largest configuration achieves 1.43x higher throughput than the state-of-the-art merge network.
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