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Exploring Slice-Energy Saving on an Video Processing FPGA Platform with Approximate Computing

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Published:27 July 2018Publication History

ABSTRACT

This paper proposes a scalable video processing platform on Field Programmable Gate Array (FPGA), providing several slice-energy cost solutions corresponding to different application constrains. Specifically three approximations of multipliers and two approximations of adders, along with the exact designs as well, are presented and integrated as twelve benchmarks to implement RGB to grayscale conversion as a case study. Experimental results show that the minimum slice-energy cost, integrated with approximate#2 adder and approximate#3 multiplier, achieves 25.17% slice-energy saving compared with the exact design by sacrificing the quality of results as 5.69% error for multiplier and 2.85% for adder.

References

  1. H. He, L. Wu, X. Yang, et al, "Dual Long Short-Term Memory Networks for Sub-Character Representation Learning," The 15th Intl. Conference on Information Technology-New Generations (ITNG), PP. 1--6, Jan. 2018.Google ScholarGoogle Scholar
  2. A. Gajjar, Y. Zhang, and X. Yang, "Demo Abstract: A Smart Building System Integrated with An Edge Computing Algorithm and IoT Mesh Networks," The Second ACM/IEEE Symposium on Edge Computing (SEC2017), No. 35, PP. 1--2, Oct. 2017. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. X. Yang, W. Wen, and M. Fan, "Improving AES Core Performance via An Advanced IBUS Protocol," ACM Journal on Emerging Technologies in Computing (ACM JETC), Vol. 14, No. 1, PP. 61--63, Jan. 2018. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. X. Yang and W. Wen, "Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)," The 22nd Asia and South Pacific Design Automation Conference (ASP-DAC 2017), PP. 1--6, Chiba, Japan, Feb. 2017.Google ScholarGoogle Scholar
  5. X. Yang, N. Wu, and J. Andrian, "A Novel Bus Transfer Mode: Block Transfer and A Performance Evaluation Methodology," Elsevier, Integration, the VLSI Journal, Vol. 52, PP. 23--33, Jan. 2016. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. X. Yang and J. Andrian, "A Low-Cost and High-Performance Embedded System Architecture and An Evaluation Methodology," IEEE Computer Society Annual Symposium on VLSI (ISVLSI2014), PP. 240--243, Sept. 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. A. Kahng and S. Kang, "Accuracy-Configurable Adder for Approximate Arithmetic Designs", The 49th Design Automation Conference (DAC2012), PP. 820--825, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Z. Kedem, V. Mooney, K. Muntimadugu, et al, "Optimizing Energy to Minimize Errors in Dataflow Graphs Using Approximate Adders", The 2010 Intl. Conference on Compilers, Architectures and Synthesis for Embedded Systems, PP. 177--186, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. M. Fan, Q. Han, and X. Yang, "Energy Minimization for On-Line Real-Time Scheduling with Reliability Awareness," Elsevier Journal of Systems and Software (JSS), Vol. 127, PP. 168--176, May 2017. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. X. Yang, N. Wu, and J. Andrian, "Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure," Journal of VLSI Design, Vol. 2017, Article ID 4914301, PP. 1--7, May 2017.Google ScholarGoogle Scholar
  11. X. Yang and J. Andrian, "A High Performance On-Chip Bus (MSBUS) Design and Verification," IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), Vol. 23, Issue: 7, PP. 1350--1354, Sept. 2015.Google ScholarGoogle Scholar
  12. Y. Zhang, X. Yang, and L. Wu, et al, "Hierarchical Synthesis of Approximate Multiplier Design for Field-Programmable Gate Arrays (FPGA)-CSRmesh System," Intl. Journal of Compt. Applications (IJCA), Vol. 180, No. 17 PP. 1--7, Feb. 2018.Google ScholarGoogle ScholarCross RefCross Ref

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  1. Exploring Slice-Energy Saving on an Video Processing FPGA Platform with Approximate Computing

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      cover image ACM Other conferences
      ICACS '18: Proceedings of the 2nd International Conference on Algorithms, Computing and Systems
      July 2018
      245 pages
      ISBN:9781450365093
      DOI:10.1145/3242840

      Copyright © 2018 ACM

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      Publication History

      • Published: 27 July 2018

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