- [AhU177] A. V. Aho and J. D. Ullman, Principles of Compiler Design, Addison-Wesley, Reading, Mass., 1977. Google ScholarDigital Library
- [AnST67] D. W. Anderson, F. J. Sparacio and R. M. Tomasulo, "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling," IBM Journal of Research and Development , pp. 8-24, January 1967.Google ScholarDigital Library
- [Back78] J. Backus, "Can programming be liberated from the von Neumann style? A functional style and its algebra of programs," Communications of the ACM, Vol. 21, No. 8, pp. 613-641, August 1978. Google ScholarDigital Library
- [Bons69] P. Bonseigneur, "Description of the 7600 Computer System," Computer Group News, pp. 11-15, May 1969.Google Scholar
- [CDC81] Control Data Corporation, CDC Cyber 200 Model 205 Computer System Hardware Reference Manual. St. Paul, Minnesota, 1981.Google Scholar
- [CeFe78] L. M. Censier and P. Feautrier, "A new solution to coherence problems in multicache systems," IEEE Trans. on Computers . Vol. C-27, No. 12, pp. 1112-1118, December 1978.Google ScholarDigital Library
- [CGKP83] G. L. Craig, J. R. Goodman. R. H. Katz, A. R. Pleszkun K. Ramachandran, J. Sayah and J. E. Smith, "PIPE: A High Performance VLSI Processor Implementation," Technical Report #513, Computer Sciences Department, University of Wisconsin-Madison, September 1983.Google Scholar
- [CoSt81] E. U. Cohler and J. E. Storer, "Functionally Parallel Architecture for Array Processors," Computer, Vol. 14, No. 9, pp. 28-36, September 1981.Google ScholarDigital Library
- [Cray82] Cray Research, Inc., Cray X-MP Series Mainframe Reference Manual. Chippewa Falls, Wisconsin, 1982.Google Scholar
- [Flyn66] M. J. Flynn, "Very High-Speed Computing Systems," Proceedings of the IEEE, Vol. 54, No. 12, pp. 1901-1909, December 1966.Google ScholarCross Ref
- [GHKP85] J. R. Goodman, J. T. Hsieh, K. Liou, A. R. Pleszkun, P. B. Schechter, and H. C. Young, "A VLSI Decoupled Architecture: PIPE," submitted to ACM Transactions of Computer Systems, March 1985.Google Scholar
- [GoYo85] J. R. Goodman and H. C. Young, "Code Scheduling Methods for Some Architectural Features in PIPE," submitted to IEEE Trans. on Computers, January 1985.Google Scholar
- [GrHe82] T. R. Gross and J. L. Hennessy, "Optimizing Delayed Branches," Proceedings, 15th Annual Workshop on Microprogramming , pp. 114-120, October, 1982. Google ScholarDigital Library
- [HLMM82] P. M. Hansen, M. A. Linton, R. N. Mayo, M. Murphy and D. A. Patterson, "A Performance Evaluation of the Intel iAPX 432," ACM Computer Architecture News, Vol. 10, No. 4, pp. 17-26, June 1982. Google ScholarDigital Library
- [Henn84] J. L. Hennessy, "VLSI Processor Architecture," IEEE Trans. on Computers, Vol. C-33, No. 12, pp. 1221-1246, December, 1984.Google Scholar
- [HJBG82] J. Hennessy, N. Jouppi, F. Baskett, T. Gross and J. Gill, "Hardware/Software Tradeoffs for Increased Performance," Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 2-11, March 1982. Google ScholarDigital Library
- [HsPG84] J. T. Hsieh, A. R. Pleszkun and J. R. Goodman, "Performance Evaluation of the PIPE Computer Architecture," Technical Report #566, Computer Sciences Department, University of Wisconsin-Madison, November 1984.Google Scholar
- [IBM74] "System/370 model 155 theory of operation/diagrams manual (Volume 5): buffer control unit," IBM System Products Division, Poughkeepsie, N. Y., 1974.Google Scholar
- [IBM76] "System/370 model 168 theory of operation/diagrams manual (Volume 1)," Document No. SY22-6931-3, IBM System Products Division, Poughkeepsie, N. Y., 1976.Google Scholar
- [KaCo81] W. J. Karplus and D. Cohen, "Architectural and Software Issues in the Design and Application of Peripheral Array Processors," Computer, Vol. 14, pp. 11-17, September 1981.Google ScholarDigital Library
- [Kung79] H. T. Kung, "Let's Design Algorithms for VLSI Systems," Proc. Conf. on VLSI: Architecture, Design, Fabrication, California Institute of Technology, January 1979.Google Scholar
- [Liou85] K. J. Liou, "Design of Pipelined Memory Systems for Decoupled Architectures" Ph.D. dissertation, University of Wisconsin-Madison, Computer Sciences Department, in preparation. Google ScholarDigital Library
- [McMa72] F. H. McMahon, "FORTRAN CPU Performance Analysis," Lawrence Livermore Laboratories, Livermore, CA, 1972.Google Scholar
- [NiFi84] A. Nicolau and J. A. Fisher, "Measuring the Parallelism Available for Very Long Instruction Word Architectures," IEEE Trans. on Computers, Vol. C-33, No. 11, pp. 968-976, November 1984.Google Scholar
- [Patt85] D. A. Patterson, "Reduced Instruction Set Computers," Communications of the ACM, Vol. 28, No. 1, pp. 8-21, January 1985. Google ScholarDigital Library
- [PaSe81] D. A. Patterson and C. H. Sequin, "RISC I: A Reduced Instruction Set VLSI Computer," Proc. of the Eighth Annual Symposium on Computer Architecture, pp. 443-458, May 1981. Google ScholarDigital Library
- [PaSe82] D. A. Patterson and C. H. Sequin, "A VLSI RISC," IEEE Computer, Vol. 15, No. 9, pp. 8-21, September 1982.Google ScholarDigital Library
- [Ples82] A. R. Pleszkun, "A Structured Memory Access Architecture," Computer Systems Group Report CSG-10, Coordinated Science Lab., Univ. of Illinois, Urbana, Illinois, October 1982.Google Scholar
- [Radi82] G. Radin, "The 801 Minicomputer," Symposium on Architectural Support for Programming Languages and Operating Systems , pp. 39-47, March 1982. Google ScholarDigital Library
- [Russ78] R. M. Russel, "The CRAY-1 Computer System," Communications of the ACM, Vol. 21, No. 1, pp. 63-72, January 1978. Google ScholarDigital Library
- [Sche77] R. W. Scheifler, "An Analysis of Inline Substitution for a Structured Programming Language," Communications of the ACM, Vol. 20, No. 9, pp. 647-654, September 1977. Google ScholarDigital Library
- [Smit84] J. E. Smith, "Decoupled Access/Execute Computer Architectures," ACM Trans. on Computer Systems, Vol. 2, No. 4, pp. 289-308, November, 1984. Google ScholarDigital Library
- [SmGo83] J. E. Smith and J. R. Goodman, "A Study of Instruction Cache Organizations and Replacement Policies," Proc. of the Tenth Annual Symposium on Computer Architecture, pp. 132- 137, June 1983. Google ScholarDigital Library
- [SPKG83] J. E. Smith, A. R. Pleszkun, R. H. Katz and J. R. Goodman, "PIPE: A High Performance VLSI Architecture," IEEE Workshop on Computer Systems Organization, New Orleans, LA, pp. 131-138, March 1983. Also available as Technical Report #512, Computer Sciences Department, University of Wisconsin-Madison, September 1983.Google Scholar
- [Tane78] A. S. Tanenbaum, "Implication of Structured Programming for Machine Architecture," Comm. ACM, Vol. 21, pp. 237- 246, March 1978. Google ScholarDigital Library
- [Thor70] J. E. Thornton, Design of a Computer--The Control Data 6600, Scott, Foreman and Co., Glenview, IL, 1970. Google ScholarDigital Library
- [WeSm84] S. Weiss and J. E. Smith, "Instruction Issue Logic in Pipelined Supercomputers," IEEE Trans. on Computers, Vol. C-33, No. 11, pp. 1013-1022, November 1984.Google Scholar
- [YoGo84a] H. C. Young and J. R. Goodman, "A Simulation Study of Architectural Data Queues and Prepare-to-branch Instruction," Proceedings, IEEE International Conference on Computer Design, pp. 544-549, October 1984.Google Scholar
- [YoGo84b] H. C. Young and J. R. Goodman, "Software Pipelining for a Pipelined Computer," Proceedings, International Computer Symposium, pp. 1251-1256, December 1984.Google Scholar
Index Terms
- PIPE: a VLSI decoupled architecture
Recommendations
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates. Based on binary trees, the MP-tree is very efficient, effective, and ...
MP-trees: a packing-based macro placement algorithm for mixed-size designs
DAC '07: Proceedings of the 44th annual Design Automation ConferenceIn this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient, effective, and flexible for handling macro placement with various ...
Comments