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Trading Between Intra- and Inter-Task Cache Interference to Improve Schedulability

Published: 10 October 2018 Publication History

Abstract

Caches help reduce the average execution time of tasks due to their fast operational speeds. However, caches may also severely degrade the timing predictability of the system due to intra- and inter-task cache interference. Intra-task cache interference occurs if the memory footprint of a task is larger than the allocated cache space or when two memory entries of that task are mapped to the same space in cache. Inter-task cache interference occurs when memory entries of two or more distinct tasks use the same cache space. State-of-the-art analysis focusing on bounding cache interference or reducing it by means of partitioning and by optimizing task layout in memory either focus on intra- or inter-task cache interference and do not exploit the fact that both intra- and inter-task cache interference can be interrelated.
In this work, we show how one can model intra- and inter-task cache interference in a way that allows balancing their respective contribution to tasks worst-case response times. Since the placement of tasks in memory and their respective cache footprint determine the intra- and inter-task interference that tasks may suffer, we propose a technique based on cache coloring to improve task set schedulability. Experimental evaluations performed using Mälardalen benchmarks show that our approach results in up to 13% higher task set schedulability than state-of-the-art approaches.

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  • (2022)PInTE: Probabilistic Induction of Theft Evictions2022 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC55918.2022.00011(1-13)Online publication date: Nov-2022
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  • (2020)Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116265(442-447)Online publication date: Mar-2020
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cover image ACM Other conferences
RTNS '18: Proceedings of the 26th International Conference on Real-Time Networks and Systems
October 2018
277 pages
ISBN:9781450364638
DOI:10.1145/3273905
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • University of Poitiers: University of Poitiers

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 October 2018

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RTNS '18
RTNS '18: 26th International Conference on Real-Time Networks and Systems
October 10 - 12, 2018
Chasseneuil-du-Poitou, France

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RTNS '18 Paper Acceptance Rate 25 of 52 submissions, 48%;
Overall Acceptance Rate 119 of 255 submissions, 47%

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Cited By

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  • (2022)PInTE: Probabilistic Induction of Theft Evictions2022 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC55918.2022.00011(1-13)Online publication date: Nov-2022
  • (2020)Cache persistence-aware memory bus contention analysis for multicore systemsProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408453(442-447)Online publication date: 9-Mar-2020
  • (2020)Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116265(442-447)Online publication date: Mar-2020
  • (2020)Bounding Cache Persistence Reload Overheads for Set-Associative Caches2020 IEEE 26th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA50079.2020.9203583(1-10)Online publication date: Aug-2020
  • (2019)Server Based Task Allocation to Reduce Inter-Task Memory Interference in Multicore Systems2019 International Conference on Frontiers of Information Technology (FIT)10.1109/FIT47737.2019.00067(322-3225)Online publication date: Dec-2019

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