skip to main content
10.1145/3286475.3286478acmotherconferencesArticle/Chapter ViewAbstractPublication PagesscConference Proceedingsconference-collections
short-paper

xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory

Published:11 November 2018Publication History

ABSTRACT

Given the switch from monolithic architectures to integrated systems of commodity components, scalable high performance computing architectures often suffer from unwanted latencies when operations depart an individual device domain. Transferring control and/or data across loosely coupled commodity devices implies a certain degree of cooperating in the form of complex system software. The end result being a total system architecture the operates in an inefficient manner.

This work presents initial research into creating micro architecture extensions to the RISC-V instruction set that provide tightly coupled support for common high performance computing operations. This xBGAS micro architecture extension provides applications the ability to access globally shared memory blocks directly from rudimentary instructions. The end result being a highly efficient micro architecture for scalable shared memory programming environments.

References

  1. {n. d.}. CCIX Consortium. https://www.ccixconsortium.com/. Accessed: 2017-09-09.Google ScholarGoogle Scholar
  2. {n. d.}. OpenCAPI Consortium. http://opencapi.org/. Accessed: 2017-09-09.Google ScholarGoogle Scholar
  3. R. H. Arpaci, D. E. Culler, A. Krishnamurthy, S. G. Steinberg, and K. Yelick. 1995. Empirical evaluation of the CRAY-T3D: a compiler perspective. In Proceedings 22nd Annual International Symposium on Computer Architecture. 320--331. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Jonathan Balkind, Michael McKeown, Yaosheng Fu, Tri Nguyen, Yanqi Zhou, Alexey Lavrov, Mohammad Shahrad, Adi Fuchs, Samuel Payne, Xiaohua Liang, Matthew Matl, and David Wentzlaff. 2016. OpenPiton: An Open Source Manycore Research Framework. In Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '16). ACM, New York, NY, USA, 217--232. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Bradford L. Chamberlain, David Callahan, and Hans P. Zima. 2007. Parallel Programmability and the Chapel Language. IJHPCA 21 (2007), 291--312. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Barbara Chapman, Tony Curtis, Swaroop Pophale, Stephen Poole, Jeff Kuehn, Chuck Koelbel, and Lauren Smith. 2010. Introducing OpenSHMEM: SHMEM for the PGAS Community. In Proceedings of the Fourth Conference on Partitioned Global Address Space Programming Model (PGAS '10). ACM, New York, NY, USA, Article 2, 3 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. GenZ Consortium. 2017. GenZ Core Specification. Technical Report. GenZ Consortium. http://genzconsortium.org/specifications/draft-core-specification-july-2017/Google ScholarGoogle Scholar
  8. UPC++ Specification Working Group. 2018. UPC++ Specification v1.0 Draft 5. Technical Report. Lawrence Berkeley National Laboratory.Google ScholarGoogle Scholar
  9. Vijay Karamcheti and Andrew A. Chien. 1995. A Comparison of Architectural Support for Messaging in the TMC CM-5 and the Cray T3D. SIGARCH Comput. Archit. News 23, 2 (May 1995), 298--307. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. John D Leidel, Xi Wang, and Yong Chen. 2017. Toward a Memory-Centric, Stacked Architecture for Extreme-Scale, Data-Intensive Computing. In Workshop On Pioneering Processor Paradigms, 2017 IEEE Symposium on High Performance Computer Architecture. IEEE.Google ScholarGoogle Scholar
  11. John D. Leidel. 2017. GoblinCore-64: A Scalable, Open Architecture for Data Intensive High Performance Computing. Ph.D. Dissertation. Texas Tech University.Google ScholarGoogle Scholar
  12. J. D. Leidel, J. Bolding, and G. Rogers. 2013. Toward a Scalable Heterogeneous Runtime System for the Convey MX Architecture. In 2013 IEEE International Symposium on Parallel Distributed Processing, Workshops and Phd Forum. 1597--1606. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. J. D. Leidel, K. Wadleigh, J. Bolding, T. Brewer, and D. Walker. 2012. CHOMP: A Framework and Instruction Set for Latency Tolerant, Massively Multithreaded Processors. In 2012 SC Companion: High Performance Computing, Networking Storage and Analysis. 232--239. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. John D. Leidel, Xi Wang, and Yong Chen. 2015. GoblinCore-64: Architectural Specification. Technical Report. Texas Tech University. http://gc64.org/wp-content/uploads/2015/09/gc64-arch-spec.pdfGoogle ScholarGoogle Scholar
  15. Arjun Menon, Subadra Murugan, Chester Rebeiro, Neel Gala, and Kamakoti Veezhinathan. 2017. Shakti-T: A RISC-V Processor with Light Weight Security Extensions. In Proceedings of the Hardware and Architectural Support for Security and Privacy (HASP '17). ACM, New York, NY, USA, Article 2, 8 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Wilfried Oed and Martin Walker. 1993. An Overview of Cray Research Computers Including the Y-MP/C90 and the New MPP T3D. In Proceedings of the Fifth Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA '93). ACM, New York, NY, USA, 271--272. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Andreas Traber, Florian Zaruba, Sven Stucki, Antonio Pullini, Germain Haugou, Eric Flamand, Frank K. Gurkaynak, and Luca Benini. 2016. PULPino: A small single-core RISC-V SoC. http://iis-projects.ee.ethz.ch/images/d/d0/Pulpino_poster_riscv2015.pdf RISC-V Workshop.Google ScholarGoogle Scholar
  18. Xi Wang, John D. Leidel, and Yong Chen. 2016. Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture. In Proceedings of the Second International Symposium on Memory Systems (MMEMSYS '16). ACM, New York, NY, USA, 177--187. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Andrew Waterman and Krste Asanovic. 2017. The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.2. Technical Report. SiFive, Inc. https://riscv.org/specifications/Google ScholarGoogle Scholar
  20. Andrew Waterman and Krste Asanovic. 2017. The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. Technical Report. SiFive, Inc. https://riscv.org/specifications/Google ScholarGoogle Scholar

Index Terms

  1. xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in
        • Published in

          cover image ACM Other conferences
          MCHPC'18: Proceedings of the Workshop on Memory Centric High Performance Computing
          November 2018
          76 pages
          ISBN:9781450361132
          DOI:10.1145/3286475

          Copyright © 2018 ACM

          © 2018 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of the United States government. As such, the United States Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 11 November 2018

          Permissions

          Request permissions about this article.

          Request Permissions

          Check for updates

          Qualifiers

          • short-paper
          • Research
          • Refereed limited

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader