research-article

AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip

Authors:

Huazhong YangAuthors Info & Claims

ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference

Pages 146 - 151

https://doi.org/10.1145/3287624.3287635

Published: 21 January 2019 Publication History

Abstract

ReRAM-based processing-in-memory (PIM) architecture is a promising solution for deep neural networks (NN), due to its high energy efficiency and small footprint. However, traditional PIM architecture has to use a separate crossbar array to store either positive or negative (P/N) weights, which limits both energy efficiency and area efficiency. Even worse, imbalance running time of different layers and idle ADCs/DACs even lower down the whole system efficiency. This paper proposes AERIS, an <u>A</u>rea/<u>E</u>nergy-efficient 1T2R <u>R</u>eRAM based processing-<u>I</u>n-memory NN <u>S</u>ystem-on-a-chip to enhance both energy and area efficiency. We propose an area-efficient 1T2R ReRAM structure to represent both P/N weights in a single array, and a reference current cancelling scheme (RCS) is also presented for better accuracy. Moreover, a layer-balance scheduling strategy, as well as the power gating technique for interface circuits, such as ADCs/DACs, is adopted for higher energy efficiency. Experiment results show that compared with state-of-the-art ReRAM-based architectures, AERIS achieves 8.5x/1.3x peak energy/area efficiency improvements in total, due to layer-balance scheduling for different layers, power gating of interface circuits, and 1T2R ReRAM circuits. Furthermore, we demonstrate that the proposed RCS compensates the non-ideal factors of ReRAM and improves NN accuracy by 5.2% in the XNOR net on CIFAR-10 dataset.

References

[1]

F Alibart, L. Gao, B. D. Hoskins, et al. 2012. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 23, 7 (2012), 075201.

[2]

Ming Cheng, Lixue Xia, Zhenhua Zhu, et al. 2017. TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks. In Design Automation Conference. 26.

Digital Library

[3]

Ping Chi, Shuangchen Li, Cong Xu, et al. 2016. PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In 2016 IEEE 43rd Annual ISCA. 27--39.

Digital Library

[4]

Kaiming He, Xiangyu Zhang, Shaoqing Ren, et al. 2016. Deep Residual Learning for Image Recognition. In IEEE Conference on Computer Vision and Pattern Recognition. 770--778.

[5]

Itay Hubara, Matthieu Courbariaux, Daniel Soudry, et al. 2016. Binarized neural networks. In Advances in neural information processing systems. 4107--4115.

Digital Library

[6]

Alex Krizhevsky. 2009. Learning Multiple Layers of Features from Tiny Images. (2009).

[7]

Alex Krizhevsky, Ilya Sutskever, and Geoffrey E. Hinton. 2012. ImageNet classification with deep convolutional neural networks. In International Conference on Neural Information Processing Systems, Vol. 25. Curran Associates Inc, 1097--1105.

Digital Library

[8]

Lukas Kull, Thomas Toifl, Martin Schmatz, et al. 2013. A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE Journal of Solid-State Circuits (2013).

[9]

Kibong Moon, Myounghoon Kwak, Jaesung Park, et al. 2017. Improved Conductance Linearity and Conductance Ratio of 1T2R Synapse Device for Neuromorphic Systems. IEEE Electron Device Letters PP, 99 (2017), 1--1.

[10]

Mohammad Rastegari, Vicente Ordonez, Joseph Redmon, et al. 2016. XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks. 525--542.

[11]

Mehdi Saberi, Reza Lotfi, Khalil Mafinezhad, et al. 2011. Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs. IEEE Transactions on Circuits and Systems I Regular Papers (2011).

[12]

Ali Shafiee, Anirban Nag, Naveen Muralimanohar, et al. 2016. ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In 2016 IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE, 14--26.

Digital Library

[13]

Wen Chao Shen, Chin Yu Mei, Y. D Chih, et al. 2012. High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process. In 2012 International Electron Devices Meeting. IEEE, 31.6.1--31.6.4.

[14]

K. Simonyan and A. Zisserman. 2014. Very Deep Convolutional Networks for Large-Scale Image Recognition. Computer Science (2014).

[15]

Linghao Song, Xuehai Qian, Hai Li, et al. 2017. PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 541--552.

[16]

Fang Su, Wei Hao Chen, Lixue Xia, et al. 2017. A 462GOPs/J RRAM-Based Nonvolatile Intelligent Processor for Energy Harvesting IoE System Featuring Nonvolatile Logics and Processing-In-Memory. In 2017 Symposium on VLSI Circuits. C260--C261.

[17]

Amr MS Tosson, Shimeng Yu, Mohab H Anis, et al. 2017. 1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. In IEEE International Conference on Asic. 12--15.

[18]

H. S. Philip Wong, Heng Yuan Lee, Shimeng Yu, et al. 2012. Metal-Oxide RRAM. Proc. IEEE (2012), 1951--1970.

[19]

Shimeng Yu, Zhiwei Li, Pai Yu Chen, et al. 2017. Binary neural network with 16 Mb RRAM macro chip for classification and online training. In International Electron Devices Meeting. 16.2.1--16.2.4.

[20]

Mahmoud Zangeneh and Ajay Joshi. 2014. Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM. IEEE TVLSI 22, 8 (2014), 1815--1828.

Cited By

Andrulis TEmer JSze V(2024)CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00012(10-23)Online publication date: 5-May-2024
https://doi.org/10.1109/ISPASS61541.2024.00012
Yue JYue J(2024)Basics and Research Status of Neural Network ProcessorsHigh Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture10.1007/978-981-97-3477-1_2(13-32)Online publication date: 1-Aug-2024
https://doi.org/10.1007/978-981-97-3477-1_2
Andrulis TEmer JSze VSolihin YHeinrich M(2023)RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!Proceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589062(1-16)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589062
Show More Cited By

Recommendations

A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor

This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using $$0.18\,\upmu \hbox {m}$$ 0.18 μ m CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential ...
A differential switched-capacitor amplifier with programmable gain and output offset voltage
SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

The design of a low-power differential Switched-Capacitor (SC) amplifier for processing a fully-differential input signal coming from a pressure sensor interface is reported. The circuit is intended to amplify the input signal, convert it to single ...
Inverter-based low-noise, 150 µW single-ended to differential SC-VGAs for second harmonic cardiac ultrasound imaging probes

This paper presents two inverter-based low-noise, low-power, single-ended to differential switched-capacitor variable gain amplifiers (SC-VGAs) for 2---6-MHz second harmonic cardiac ultrasound imaging probes fabricated with 0.18 µm complementary metal---...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference

January 2019

794 pages

ISBN:9781450360074

DOI:10.1145/3287624

General Chair:
Toshiyuki Shibuya
Fujitsu Laboratories

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IEEE CAS
IEEE CEDA
IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2019

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Funding Sources

National Natural Science Foundation of China
Beijing Innovation Center for Future Chip

Conference

ASPDAC '19

Sponsor:

SIGDA

ASPDAC '19: 24th Asia and South Pacific Design Automation Conference

January 21 - 24, 2019

Tokyo, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
418
Total Downloads

Downloads (Last 12 months)24
Downloads (Last 6 weeks)1

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Andrulis TEmer JSze V(2024)CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00012(10-23)Online publication date: 5-May-2024
https://doi.org/10.1109/ISPASS61541.2024.00012
Yue JYue J(2024)Basics and Research Status of Neural Network ProcessorsHigh Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture10.1007/978-981-97-3477-1_2(13-32)Online publication date: 1-Aug-2024
https://doi.org/10.1007/978-981-97-3477-1_2
Andrulis TEmer JSze VSolihin YHeinrich M(2023)RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!Proceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589062(1-16)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589062
Han LHuang PZhou ZChen YLiu XKang J(2023)A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247977(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247977
Yue JLiu YYuan ZFeng XHe YSun WZhang ZSi XLiu RWang ZChang MDou CLi XLiu MYang H(2022)STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data ReuseIEEE Journal of Solid-State Circuits10.1109/JSSC.2022.314827357:8(2560-2573)Online publication date: Aug-2022
https://doi.org/10.1109/JSSC.2022.3148273
Yu SZhang LWang JYue JYuan ZLi XYang HLiu Y(2021)High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA)10.1109/NVMSA53655.2021.9628683(1-6)Online publication date: 18-Aug-2021
https://doi.org/10.1109/NVMSA53655.2021.9628683
Zhang ZLi YYang LLi JMiao X(2021)In-Memory Hamming Distance Calculation Based on One- Transistor-Two-Memristor (1T2M) Structure2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)10.1109/EDTM50988.2021.9420835(1-3)Online publication date: 8-Apr-2021
https://doi.org/10.1109/EDTM50988.2021.9420835
Wang CFeng DTong WLiu JLi ZChang JZhang YWu BXu JZhao WLi YRen R(2019)Cross-point Resistive MemoryACM Transactions on Design Automation of Electronic Systems10.1145/332506724:4(1-37)Online publication date: 20-Jun-2019
https://dl.acm.org/doi/10.1145/3325067

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten