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View all- Antoniou GBartolini DVolos HKleanthous MWang ZKalaitzidis KRollet TLi ZMutlu OSazeides YHaj Yahya J(2024)Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start LatencyACM Transactions on Architecture and Code Optimization10.1145/367473421:4(1-26)Online publication date: 2-Jul-2024
- Yahya JVolos HBartolini DAntoniou GKim JWang ZKalaitzidis KRollet TChen ZGeng YMutlu OSazeides Y(2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00063(835-850)Online publication date: Oct-2022
- Groma MMacko D(2021)Simplified introduction of power intent into a register-transfer level modelDesign Automation for Embedded Systems10.1007/s10617-021-09254-wOnline publication date: 15-Aug-2021