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Fully-automated synthesis of power management controllers from UPF

Published: 21 January 2019 Publication History

Abstract

We present a methodology for automatic synthesis of power management controllers for System-on-Chip designs by using an extended version of the Unified Power Format (UPF). Our methodology takes an SoC design and a UPF-based power design, and automatically generates a power management controller in Verilog/VHDL that implements the power state machine specified in UPF. It performs a priority-based scheduling for all power state machine actions, connects each power management signal to the corresponding logic wire in the UPF design and integrates the controller into the System-on-Chip using a configurable bus interface. We implemented the proposed approach as a plugin for Synopsys Design Compiler to close the gap in today's power management flows and evaluated it by a RISC-V System-on-Chip.

References

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IEEE Computer Society, IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems. 2015.
[2]
V. Melikyan, T. Hakhverdyan, S. Manukyan, A. Gevorgyan, and D. Babayan, "Low power OpenRISC processor with power gating, multi-VTH and multi-voltage techniques," IEEE East-West Design & Test Symposium (EWDTS), 2016.
[3]
V. Gourisetty, H. Mahmoodi, V. Melikyan, E. Babayan, R. Goldman, K. Holcomb, and T. Wood, "Low power design flow based on Unified Power Format and Synopsys tool chain," Proceedings of the 3rd Interdisciplinary Engineering Design Education Conference, IEDEC, 2013.
[4]
B. Wang, Y. Xu, R. Hasholzner, C. Drewes, I. D. Gmbh, R. Rosales, S. Graf, and J. Falk, "Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design," Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Signalen und Systemen, 2016.
[5]
O. Mbarek, A. Khecharem, A. Pegatoquet, and M. Auguin, "Using model driven engineering to reliably accelerate early Low Power Intent Exploration for a system-on-chip design," Proceedings of the 27th Annual ACM Symposium on Applied Computing, 2012.
[6]
O. Mbarek, A. Pegatoquet, and M. Auguin, "Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction level," IET Circuits, Devices & Systems, 2012.
[7]
Dominik Macko, "System-Level Power Management Specification," in PAD 2013 Počítačové architektury & diagnostika, 2013.
[8]
C. Papon, "SpinalHDL: An alternative hardware description language," FOSDEM, 2017.
[9]
Synopsys, "32/28nm Generic Library," 2015.
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GLOBALFOUNDRIES, "22FDX - 22nm FD-SOI Technology," 2016.

Cited By

View all
  • (2024)Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start LatencyACM Transactions on Architecture and Code Optimization10.1145/367473421:4(1-26)Online publication date: 2-Jul-2024
  • (2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00063(835-850)Online publication date: Oct-2022
  • (2021)Simplified introduction of power intent into a register-transfer level modelDesign Automation for Embedded Systems10.1007/s10617-021-09254-wOnline publication date: 15-Aug-2021

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cover image ACM Conferences
ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference
January 2019
794 pages
ISBN:9781450360074
DOI:10.1145/3287624
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IEEE CAS
  • IEEE CEDA
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2019

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Author Tags

  1. power design
  2. power management
  3. unified power format

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Cited By

View all
  • (2024)Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start LatencyACM Transactions on Architecture and Code Optimization10.1145/367473421:4(1-26)Online publication date: 2-Jul-2024
  • (2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00063(835-850)Online publication date: Oct-2022
  • (2021)Simplified introduction of power intent into a register-transfer level modelDesign Automation for Embedded Systems10.1007/s10617-021-09254-wOnline publication date: 15-Aug-2021

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