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Finding placement-relevant clusters with fast modularity-based clustering

Published: 21 January 2019 Publication History

Abstract

In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies it would be very valuable to better predict final placement of the gate-level netlist: this would enable more accurate early assessment of performance, congestion and floorplan viability in the SOC floorplanning/RTL planning stages of design. In this work, we study a new criterion for the classic challenge of VLSI netlist clustering: how well netlist clusters "stay together" through final implementation. We propose use of several evaluators of this criterion. We also explore the use of modularity-driven clustering to identify natural clusters in a given graph without the tuning of parameters and size balance constraints typically required by VLSI CAD partitioning methods. We find that the netlist hypergraph-to-graph mapping can significantly affect quality of results, and we experimentally identify an effective recipe for weighting that also comprehends topological proximity to I/Os. Further, we empirically demonstrate that modularity-based clustering achieves better correlation to actual netlist placements than traditional VLSI CAD methods (our method is also 4X faster than use of hMetis for our largest testcases). Finally, we show a potential flow with fast "blob placement" of clusters to evaluate netlist and floorplan viability in early design stages; this flow can predict gate-level placement of 370K cells in 200 seconds on a single core.

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  1. Finding placement-relevant clusters with fast modularity-based clustering

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    cover image ACM Conferences
    ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference
    January 2019
    794 pages
    ISBN:9781450360074
    DOI:10.1145/3287624
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    Published: 21 January 2019

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    • (2024)FLIP: An Artificial Neural Network-based Post-routing Incremental Placer2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00014(55-60)Online publication date: 6-Jan-2024
    • (2024)Swarm - A VLSI Timing, Fanout-aware Clustering Algorithm2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528366(1-8)Online publication date: 3-Apr-2024
    • (2023)Progress of Placement Optimization for Accelerating VLSI Physical DesignElectronics10.3390/electronics1202033712:2(337)Online publication date: 9-Jan-2023
    • (2023)Placement Initialization via Sequential Subspace Optimization with Sphere ConstraintsProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3571877(133-140)Online publication date: 26-Mar-2023
    • (2022)A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design AutomationACM Transactions on Design Automation of Electronic Systems10.1145/356339128:2(1-57)Online publication date: 13-Sep-2022
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    • (2021)The Law of AttractionProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447045(7-14)Online publication date: 22-Mar-2021
    • (2021)A graph placement methodology for fast chip designNature10.1038/s41586-021-03544-w594:7862(207-212)Online publication date: 9-Jun-2021
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