skip to main content
10.1145/3287624.3287700acmconferencesArticle/Chapter ViewAbstractPublication PagesaspdacConference Proceedingsconference-collections
research-article

Exploring emerging CNFET for efficient last level cache design

Published: 21 January 2019 Publication History

Abstract

Carbon Nanotube field-effect transistors (CNFET) emerge as a promising alternative to the conventional CMOS for the much higher speed and power efficiency. It is particularly suitable for building the power-hungry last level cache (LLC). However, the process variation (PV) in CNFET substantially affects the operation stability and thus the worst-case timing, which limits the LLC operation frequency dramatically given a fully synchronous design. To address this problem, we developed a variation-aware cache such that each part of the cache can run at its optimal frequency and the overall cache performance can be improved significantly.
While asymmetric-correlated in the variation unique to the CNFET fabrication process, this indicates that cache latency distribution is closely related with the LLC layouts. For the two typical LLC layouts, we proposed variation-aware-set (VAS) cache and variation-aware-way (VAW) cache respectively to make best use of the CNFET cache architecture. For VAS cache, we further proposed a static page mapping to ensure the most frequent used data are mapped to the fast cache region. Similarly, we apply a latency-aware LRU replacement strategy to assign the most recent data to the fast cache region. According to the experiments, the optimized CNFET based LLC improves the performance by 39% and reduces the power consumption by 10% on average compared to the baseline CNFET LLC design.

References

[1]
Song L, Wang Y, Han Y, et al. C-brain:a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization{J}. 2016:1--6.
[2]
Wang Y, Xu J, Han Y, et al. DeepBurning: Automatic generation of FPGA-based learning accelerators for the Neural Network family{C} Design Automation Conference. IEEE, 2016:1--6.
[3]
Zang W, et al. A survey on cache tuning from a power/energy perspective {J} . Acm Computing Surveys, 2013, 45(3):1--49.
[4]
Patil N, Lin A, Zhang J, et al. Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions{C} Design Automation Conference, 2009. DAC '09. ACM/ IEEE. IEEE, 2009:304--309.
[5]
Zhang J, et al. Carbon nanotube circuits in the presence of carbon nanotube density variations{C} Design Automation Conference, 2009. DAC'09. ACM/IEEE. IEEE, 2009:71--76.
[6]
Zhang J, et al. Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits{M}. IEEE Press, 2009.
[7]
Zhang J, Patil N, Wong H S P, et al. Overcoming carbon nanotube variations through co-optimized technology and circuit design{C} Electron Devices Meeting. IEEE, 2012:4.6.1--4.6.4.
[8]
Zhang J, Bobba S, Patil N, et al. Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement {J}. 2010, 1:889 -- 892.
[9]
Li J, Li T, Jing N, et al. CNFET-Based High Throughput SIMD Architecture{J}. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, PP(99):1--1.
[10]
Li T, et al. On microarchitectural modeling for CNFET-based circuits{C} IEEE International System-On-Chip Conference. IEEE, 2015:356--361.
[11]
Bennaser M, Guo Y, et al. Data Memory Subsystem Resilient to Process Variations{J}. IEEE Transactions on Very Large Scale Integration Systems, 2008, 16(12):1631--1638.
[12]
A. Lin et al. ACCNT: A metallic-CNT-tolerant design methodology for carbon-nanotube VLSI: Analyses and design guideline. IEEE Trans. Electron Devices, 56(12):2969--2978, 2009.
[13]
Beste M, et al. Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits{C}International Conference on Vlsi Design and 2014, International Conference on Embedded Systems. IEEE, 2014:393--398.
[14]
Zhang Z, Delgado-Frias J G. Carbon Nanotube SRAM Design With Metallic CNT or Removed Metallic CNT Tolerant Approaches {J}. IEEE Transactions on Nanotechnology, 2012, 11(4):788--798.
[15]
Xie F, et al. Jump test for metallic CNTs in CNFET-based SRAM{C} Acm/edac/ieee Design Automation Conference. IEEE, 2015:1--6.
[16]
Kim N S, Wang H. Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices{M}. IEEE Computer Society Press, 2013.
[17]
Shulaker M . et al. Carbon nanotube computer{J}. Nature, 2013, 501(7468):526.
[18]
Huang R F, Lai Y T, Chou Y F, et al. SRAM delay fault modeling and test algorithm development{M}. 2004.
[19]
Zhang J, Patil N P, et al. Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations{J}. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(8):1103--1113.
[20]
J. Lin, et.al . Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. In Proceedings of the 14th International Symposium on High Performance Computer Architecture, pages 367--378, 2008.

Cited By

View all
  • (2023)IntroductionBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design10.1007/978-981-19-8551-5_1(1-31)Online publication date: 2-Mar-2023
  • (2022)Taming Process Variations in CNFET for Efficient Last-Level Cache DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.313550230:4(418-431)Online publication date: Apr-2022
  • (2020)CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116395(963-966)Online publication date: Mar-2020

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference
January 2019
794 pages
ISBN:9781450360074
DOI:10.1145/3287624
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

In-Cooperation

  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IEEE CAS
  • IEEE CEDA
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2019

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Research-article

Conference

ASPDAC '19
Sponsor:

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)1
  • Downloads (Last 6 weeks)0
Reflects downloads up to 15 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2023)IntroductionBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design10.1007/978-981-19-8551-5_1(1-31)Online publication date: 2-Mar-2023
  • (2022)Taming Process Variations in CNFET for Efficient Last-Level Cache DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.313550230:4(418-431)Online publication date: Apr-2022
  • (2020)CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116395(963-966)Online publication date: Mar-2020
  • (2020)Carbon Nanotube Length Variation in Correlated CNFETs2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO)10.1109/NANO47656.2020.9183538(57-61)Online publication date: Jul-2020

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media