Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS
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- IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
- IEEE CAS
- IEEE CEDA
- IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology
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Association for Computing Machinery
New York, NY, United States
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