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Integrated flow for reverse engineering of nanoscale technologies

Published: 21 January 2019 Publication History

Abstract

In view of potential risks of piracy and malicious manipulation of complex integrated circuits built in technologies of 45 nm and less, there is an increasing need for an effective and efficient process of reverse engineering. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the extraction of a layout. For the first time the error between the generated layout and the known drawn GDS will be compared quantitatively as a figure of merit (FOM). From this layout a circuit graph of an ECC encryption and the partitioning in circuit blocks will be extracted.

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  • (2025)Segmentation of IC Images in Integrated Circuit Reverse Engineering Using EfficientNet Encoder Based on U‐Net++ ArchitectureInternational Journal of Circuit Theory and Applications10.1002/cta.4485Online publication date: 21-Feb-2025
  • (2024)HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00020(133-149)Online publication date: 29-Jun-2024
  • (2024)HAWKEYE – Recovering Symmetric Cryptography From Hardware CircuitsAdvances in Cryptology – CRYPTO 202410.1007/978-3-031-68385-5_11(340-376)Online publication date: 18-Aug-2024
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cover image ACM Conferences
ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference
January 2019
794 pages
ISBN:9781450360074
DOI:10.1145/3287624
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IEEE CAS
  • IEEE CEDA
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2019

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Author Tags

  1. chip scanning
  2. image processing
  3. netlist extraction
  4. reverse engineering

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all
  • (2025)Segmentation of IC Images in Integrated Circuit Reverse Engineering Using EfficientNet Encoder Based on U‐Net++ ArchitectureInternational Journal of Circuit Theory and Applications10.1002/cta.4485Online publication date: 21-Feb-2025
  • (2024)HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00020(133-149)Online publication date: 29-Jun-2024
  • (2024)HAWKEYE – Recovering Symmetric Cryptography From Hardware CircuitsAdvances in Cryptology – CRYPTO 202410.1007/978-3-031-68385-5_11(340-376)Online publication date: 18-Aug-2024
  • (2023)CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse EngineeringInformation10.3390/info1412065614:12(656)Online publication date: 11-Dec-2023
  • (2023)Leaking Wireless ICs via Hardware Trojan-Infected SynchronizationIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2022.321850720:5(3845-3859)Online publication date: 1-Sep-2023
  • (2023)No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)10.1109/IPFA58228.2023.10249049(1-9)Online publication date: 24-Jul-2023
  • (2022)REFICS: A Step Towards Linking Vision with Hardware Assurance2022 IEEE/CVF Winter Conference on Applications of Computer Vision (WACV)10.1109/WACV51458.2022.00352(3461-3470)Online publication date: Jan-2022
  • (2022)Digital-to-Analog Hardware Trojan AttacksIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.311680669:2(573-586)Online publication date: Feb-2022
  • (2022)Digitally Assisted Mixed-Signal Circuit SecurityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.311155041:8(2449-2462)Online publication date: Aug-2022
  • (2022)Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis2022 25th Euromicro Conference on Digital System Design (DSD)10.1109/DSD57027.2022.00073(504-512)Online publication date: Aug-2022
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