research-article

Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer

Authors:

Nima Karimpour Darav,

Andrew Kennings,

Kristofer Vorwerk,

Arun KunduAuthors Info & Claims

FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 122 - 131

https://doi.org/10.1145/3289602.3293896

Published: 20 February 2019 Publication History

Abstract

Modern analytic placement tools are commonly built around the idea of iterative Lower Bound (LB) and Upper Bound (UB) placement. The LB step optimizes wirelength and timing while ignoring overlap and cell-type constraints, whereas the UB step attempts to spread cells and satisfy constraints without harming design quality. Top-down geometric partitioning techniques have traditionally been used to spread cells during UB placement. We propose a new, network flow-based approach for UB placement which does a better job of preserving quality by optimizing the displacement of cells from their LB positions. Our approach not only addresses cell overlap, but also accommodates complex region constraints and simultaneously spreads unit-sized logic, carry chains, and blocks like RAMs and DSPs. Our technique is scalable, does not require geometric partitioning, and is suitable for both flat and clustered placement flows.We deployed our algorithm in a commercial FPGA CAD flow, and show that it reduces HPWL by 6.4% on average (up to 22.8% in the best case) while improving worst-slack timing in over 90% of designs, compared to a state-of-the-art alternative.

References

[1]

R. K. Ahuja, T. L. Magnanti, and J. B. Orlin. 1993. Network Flows: Theory, Algorithms, and Applications .Prentice-Hall, Inc., Upper Saddle River, NJ, USA.

Digital Library

[2]

V. Betz and J. Rose. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proc. FPL . 213--222.

Digital Library

[3]

R.C. Cofer and B.F. Harding. 2006. Rapid System Prototyping with FPGAs: Accelerating the Design Process .Elsevier Science. 146--147 pages.

Digital Library

[4]

Microsemi Corporation. 2017. PO0137 Product Overview PolarFire FPGA. Microsemi Corp., San Jose, CA.

[5]

N. K. Darav, I. S. Bustany, A. Kennings, D. Westwick, and L. Behjat. 2018. Eh"Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints. TODAES, Vol. 23, 4 (2018), 43:1--43:25.

Digital Library

[6]

N. K. Darav, A. Kennings, A. F. Tabrizi, D Westwick, and L. Behjat. 2016. Eh-Placer: A high-performance modern technology-driven Placer. TODAES, Vol. 21, 3 (April 2016), 37:1--37:27.

Digital Library

[7]

Hans Eisenmann and Frank M. Johannes. 1998. Generic Global Placement and Floorplanning. In Proc. DAC. 269--274.

Digital Library

[8]

W. Feng, J. Greene, K. Vorwerk, V. Pevzner, and A. Kundu. 2014. Rent's rule based FPGA packing for routability optimization. In Proc. FPGA . 31--34.

Digital Library

[9]

M. Gort and J. H. Anderson. 2012. Analytic placement for heterogeneous FPGAs. In Proc. FPL. 143--150.

[10]

X. He, T. Huang, L. Xiao, H. Tian, and E. F. Y. Young. 2013. Ripple: A robust and effective routability-driven placer. TCAD, Vol. 32, 10 (October 2013), 1546--1556.

Digital Library

[11]

M. C. Kim, D. J. Lee, and I. L. Markov. 2012. SimPL: An effective placement algorithm. TCAD, Vol. 31, 1 (Jan 2012), 50--60.

Digital Library

[12]

W. Li, S. Dhar, and D. Z. Pan. 2018. UTPlaceF: A routability-driven FPGA placer with physical and congestion aware packing. TCAD, Vol. 37, 4 (April 2018), 869--882.

Digital Library

[13]

T. Lin, C. Chu, J. R. Shinnerl, I. Bustany, and I. Nedelchev. 2015. POLAR: A high performance mixed-size wirelengh-driven placer with density constraints. TCAD, Vol. 34, 3 (March 2015), 447--459.

[14]

P. Maidee, C. Ababei, and B. Bazargan. 2005. Timing-driven partitioning-based placement for island style FPGAs. TCAD, Vol. 24, 3 (2005), 395--406.

Digital Library

[15]

R. Pattison, Z. Abuowaimer, S. Areibi, G. Grewal, and A. Vannelli. 2016. GPlace: A congestion-aware placement tool for UltraScale FPGAs. In Proc. ICCAD . 1--7.

Digital Library

[16]

C-W Pui, G. Chen, W-K. Chow, K-C. Lam, J. Kuang, P. Tu, H. Zhang, E. F. Y. Young, and B. Yu. 2016. RippleFPGA: A Routability-driven Placement for Large-scale Heterogeneous FPGAs. In Proc. ICCAD . 1--8.

Digital Library

[17]

Yang S., A. Gayasen, C. Mulpuri, S. Reddy, and R. Aggarwal. 2016. Routability-driven FPGA placement contest. In Proc. ISPD. 139--143.

Digital Library

[18]

Yang S., C. Mulpuri, S. Reddy, M. Kalase, S. Dasasathyan, M. E. Dehkordi, M. Tom, and R. Aggarwal. 2017. Clock-aware FPGA placement contest. In Proc. ISPD. 159--164.

Digital Library

[19]

P. Spindler and F. M. Schlichtmann, U. Johannes. 2008. Kraftwerk2: A fast force-directed quadratic placement approach using an accurate net model. TCAD, Vol. 27, 8 (Aug 2008), 1398--1411.

Digital Library

[20]

D. Vercruyce, E. Vansteenkiste, and D. Stroobandt. 2018. Hierarchical force-based block spreading for analytic FPGA placement. In Proc. FPL .

Cited By

Nikolić SNikolić S(2025)Dedicated Placement for Fixed-Connectivity PatternsModern Programmable Interconnect Design10.1007/978-3-031-80629-2_8(237-282)Online publication date: 7-Mar-2025
https://doi.org/10.1007/978-3-031-80629-2_8
Thurmer KBetz V(2024)VIPER: A VTR Interface for Placement with Error ResilienceProceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3665283.3665300(99-108)Online publication date: 19-Jun-2024
https://dl.acm.org/doi/10.1145/3665283.3665300
Yu TDarav NBustany IDehkordi MBadaroglu MDutt S(2022)A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA'sProceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding10.1145/3557988.3569714(1-7)Online publication date: 3-Nov-2022
https://dl.acm.org/doi/10.1145/3557988.3569714
Show More Cited By

Recommendations

Implementation and extensibility of an analytic placer

Automated cell placement is a critical problem in very large scale integration (VLSI) physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently received much attention from both academia and ...
Implementation and extensibility of an analytic placer
ISPD '04: Proceedings of the 2004 international symposium on Physical design

Automated cell placement is a critical problem in VLSI physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently received much attention from both academia and industry. A novel and simple ...
Timing-driven partitioning-based placement for island style FPGAs

In traditional field programmable gate array (FPGA) placement methods, there is virtually no coupling between placement and routing. Performing simultaneous placement and detailed routing has been shown to generate much better placement qualities, but ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2019

360 pages

ISBN:9781450361378

DOI:10.1145/3289602

General Chair:
Kia Bazargan
Univ. of Minnesota, USA
,
Program Chair:
Stephen Neuendorffer
Xilinx, USA

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 February 2019

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

FPGA '19

Sponsor:

SIGDA

FPGA '19: The 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 24 - 26, 2019

CA, Seaside, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
389
Total Downloads

Downloads (Last 12 months)27
Downloads (Last 6 weeks)3

Reflects downloads up to 03 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Nikolić SNikolić S(2025)Dedicated Placement for Fixed-Connectivity PatternsModern Programmable Interconnect Design10.1007/978-3-031-80629-2_8(237-282)Online publication date: 7-Mar-2025
https://doi.org/10.1007/978-3-031-80629-2_8
Thurmer KBetz V(2024)VIPER: A VTR Interface for Placement with Error ResilienceProceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3665283.3665300(99-108)Online publication date: 19-Jun-2024
https://dl.acm.org/doi/10.1145/3665283.3665300
Yu TDarav NBustany IDehkordi MBadaroglu MDutt S(2022)A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA'sProceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding10.1145/3557988.3569714(1-7)Online publication date: 3-Nov-2022
https://dl.acm.org/doi/10.1145/3557988.3569714
Nikolić SZgheib GIenne P(2022)Detailed Placement for Dedicated LUT-Level FPGA InterconnectACM Transactions on Reconfigurable Technology and Systems10.1145/350180215:4(1-33)Online publication date: 9-Dec-2022
https://dl.acm.org/doi/10.1145/3501802
Meng YLi WLin YPan D(2022)elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305319141:1(155-168)Online publication date: Jan-2022
https://doi.org/10.1109/TCAD.2021.3053191
Nikolic SZgheib GIenne P(2020)Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00035(153-161)Online publication date: Aug-2020
https://doi.org/10.1109/FPL50879.2020.00035

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten