ABSTRACT
Placement is a crucial step in the FPGA design tool flow, as it determines the overall performance of the circuits. Unfortunately, it is a time-consuming task. Analytical placers have been shown to be the most time-efficient while retaining good quality. One way of implementing analytical placement is to use an iterative technique that consists of optimization and look-ahead legalization, followed by an optional refinement step. In this work, with the aim towards fast hard block legalization for further accelerating analytical placement, a novel optimizer is proposed based on the modified discrete adaptive particle swarm optimization. The proposed optimizer is embedded into the publicly available analytical placer Liquid. When compared to its version using simulated annealing for hard block legalization, this approach results in a 30% reduction in hard block legalization time and a consequent 5% runtime reduction for the analytical placement, at the cost of only a 1% increase in post-routed wirelength and critical path delay. The results indicate that the nature-inspired particle swarm optimization is promising for tackling such a problem with new learning strategies and adaptation.
Index Terms
- MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA Placement
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