Building FPGA State Machines from Sequential Code

State machines are commonly used and well understood for hardware. However, in some cases they can introduce complexity as the program can no longer be read sequentially. We propose an extension to the SME model, which retains the sequential program structure, by using a barrier-like 'await' construct to divide a program into states. This is done by awaiting a predicate, ensuring that the sequential program does not progress until the predicate is satisfied. This initial implementation enables the clock signal as a predicate, allowing for easy partitioning of the sequential program, which is a common approach when either pipelining or sequencing a problem. Future implementations will also enable functions or signal values as predicates. The signal values will be a simple to use barrier when waiting for external input. As for the functions, it handles all the communication regarding input/output for and synchronization with the function. As always with the SME model, the problems implemented in the model can be transpiled into VHDL along with a VHDL test bench, which verifies that the generated VHDL matches the SME simulation. Our preliminary results shows that Xilinx Vivado recognises the state machines and that the SME simulation is clock cycle accurate to the simulation of the generated VHDL. Furthermore, we see reduced resource consumption and higher clock rates, as we should by leveraging state machines, without increasing the complexity and readability of the original program.