ABSTRACT
Translation validation is the process of proving that the target code is a correct translation of the source program being compiled. In this work, we propose a translation validation method to verify code motion transformations involving loops applied during the scheduling phase of high-level synthesis (HLS). Our method is capable of ignoring false computations during translation validation. In this work, we show that how to generate a counter-trace (cTrace) using the internal information of verifier in the case of non-equivalence reported by a translation validation method. We also show how a Bounded Model Checker (CBMC) can be used to find a counterexample for a given cTrace. Experimental results demonstrate the usefulness of our method.
- Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, and Chittaranjan A. Mandal. 2014. Verification of Code Motion Techniques Using Value Propagation. IEEE TCAD 33, 8 (Aug 2014), 1180--1193.Google Scholar
- Ramanuj Chouksey, Chandan Karfa Kunal Banerjee, Pankj Kalita, and Purandar Bhaduri. forthcoming. A Counter-Example Generation Procedure for Path based Equivalence Checkers. IET Softeware (forthcoming).Google Scholar
- Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri. 2017. Translation Validation of Loop Invariant Code Optimizations Involving False Computations. In VDAT. 767--778.Google Scholar
- Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri. 2018. Translation Validation of Code Motion Transformations Involving Loops. IEEE TCAD (2018).Google Scholar
- Ramanuj Chouksey, Chandan Karfa, and Purandar Bhaduri. forthcoming. Improving Performance of a Path-Based Equivalence Checker using Counter-Examples. In VLSID.Google Scholar
- Edmund Clarke, Daniel Kroening, and Flavio Lerda. 2004. A Tool for Checking ANSI-C Programs. In Tools and Algorithms for the Construction and Analysis of Systems. Springer, Berlin, Heidelberg, 168--176.Google Scholar
- Leonardo Mendonça de Moura and Nikolaj Bjørner. 2008. Z3: An Efficient SMT Solver. In Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2008 (LNCS), Vol. 4963. Springer, Berlin, Heidelberg, 337--340. Google ScholarDigital Library
- Robert W Floyd. 1967. Assigning meanings to programs. Mathematical aspects of computer science 19, 1 (1967), 19--32.Google Scholar
- Daniel D. Gajski, Nikil D. Dutt, Allen C.-H. Wu, and Steve Y.-L. Lin. 1992. High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, Norwell, MA, USA. Google ScholarDigital Library
- S. Gupta, N. Dutt, R. Gupta, and A. Nicolau. 2003. SPARK: A high-level synthesis framework for applying parallelizing compiler transformations. In Proceedings, VLSID. IEEE, 461--466. Google ScholarDigital Library
- Chandan Karfa, Chittaranjan A. Mandal, and Dipankar Sarkar. 2012. Formal verification of code motion techniques using dataflow-driven equivalence checking. ACM TODAES 17, 3 (Jul 2012), 30. Google ScholarDigital Library
- Chandan Karfa, Dipankar Sarkar, Chitta Mandal, and P. Kumar. 2008. An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE TCAD 27, 3 (Mar 2008), 556--569. Google ScholarDigital Library
- Youngsik Kim, Shekhar Kopuri, and Nazanin Mansouri. 2004. Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD). In ISQED 2004. IEEE Computer Society, 110--115. Google ScholarDigital Library
- Chris Lattner and Vikram Adve. 2004. LLVM: A compilation framework for lifelong program analysis & transformation. In CGO 2004. IEEE, 129--142. Google ScholarDigital Library
Index Terms
- Formal Verification of Optimizing Transformations during High-level Synthesis
Recommendations
Formal verification of code motion techniques using data-flow-driven equivalence checking
Special section on verification challenges in the concurrent worldA formal verification method for checking correctness of code motion techniques is presented in this article. Finite State Machine with Datapath (FSMD) models have been used to represent the input and the output behaviors of each synthesis step. The ...
Hand-in-hand verification of high-level synthesis
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSIThis paper describes a formal verification methodology of high-level synthesis (HLS) process. The abstraction level of the input to HLS is so high compared to thatof the output that the verification has to proceed hand-in-hand with the synthesis ...
Comments