ABSTRACT
Routing for dense circuits is a major challenge for VLSI physical design. Most routing approaches rely at least partially on a "rip-up and reroute" scheme, where solution quality and run times can be impacted profoundly by the order in which nets are routed. Other routing tools rely on backtracking methods embedded in integer linear programming solvers. In this paper, we present a novel approach which avoids backtracking, and largely eliminates the routing order considerations, by constructing a large number of routings simultaneously. By keeping "options open," our approach sidesteps conflicts. Our approach is a factor of ten faster than other recent work, reduces via counts by 30% or more, and is competitive on both wire length and completion rates. The approach is simple, scalable, and adaptable to the complex constraints of modern circuit fabrication processes.
- D. N. Deutsch. Compacted channel routing. In Proc. Int. Conf. on Computer Aided Design, pages 223--225, 1985.Google Scholar
- J. P. Cohoon and P. L. Heck. Beaver: a computational geometry based tool for switchbox routing. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 7:684--697, 1988. Google ScholarDigital Library
- E. Dijkstra. A note on two problems in connexion with graphs. Numerische Mathematik, 1:269--271, 1959. Google ScholarDigital Library
- W. A. Dees and R. J. Smith. Performance of interconnection rip-up and reroute strategies. In Proc. Design Automation Conference, pages 382--390, 1981. Google ScholarDigital Library
- L. McMurchie and C. Ebeling. Pathfinder: a negotiation-based performance-driven router for FPGAs. In Proc. Int. Symp. on Field-Programmable Gate Arrays, pages 111--117, 1995. Google ScholarDigital Library
- C. Mead and L. Conway. Introduction to VLSI Systems. Addison-Wesley, 1993. Google ScholarDigital Library
- Nikolai Ryzhenko and Steven Burns. Standard cell routing via boolean satisfiability. In Proceedings of the 49th Annual Design Automation Conference, pages 603--612. ACM, 2012. Google ScholarDigital Library
- Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, and David Z Pan. PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning. ACM Trans. Design Automation of Electronic Systems, 21(3):42:1--42:21, 2016. Google ScholarDigital Library
- Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, and David Z. Pan. DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. In Proceedings of the 2017 ACM on International Symposium on Physical Design, pages 91--98. ACM, 2017. Google ScholarDigital Library
- Iou Jen Liu, Shao Yun Fang, and Yao Wen Chang. Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(9):1519--1531, 2016.Google ScholarCross Ref
- R. G. Wood and R. A. Rutenbar. FPGA routing and routability estimation via boolean satisfiability. In FPGA, pages 119--125, 1997. Google ScholarDigital Library
- R. Kastner, E. Bozogzadeh, and M. Sarrafzadeh. Predictable routing. Proc. Int. Conf. on Computer Aided Design, pages 110--113, 2000. Google ScholarDigital Library
- Y. Zhang and C. Chu. RegularRoute: An efficient detailed router applying regular routing patterns. Trans. VLSI Systems, 21(9):1655--1668, 2013. Google ScholarDigital Library
- Yuelin Du, Zigang Xiao, Martin DF Wong, He Yi, and H-S Philip Wong. Dsa-aware detailed routing for via layer optimization. In Alternative Lithographic Technologies VI, volume 9049, page 90492J. International Society for Optics and Photonics, 2014.Google Scholar
Index Terms
- HydraRoute: A Novel Approach to Circuit Routing
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