research-article

A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network

Authors:

Yu Pan,

Weisheng ZhaoAuthors Info & Claims

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

Pages 271 - 274

https://doi.org/10.1145/3299874.3318015

Published: 13 May 2019 Publication History

Get Access

Abstract

A Skyrmion Racetrack Memory (SRM) based Computing In-Memory Architecture (SRM-CIM) was proposed in this paper. Both data and computing operation can be achieved in SRM-CIM. SRM-CIM is used to support convolutional computing in Binary Convolutional Neural Network (BCNN). Experimental results show that SRM-CIM achieves 98.7% and 82% energy reduction when compared with RRAM and SOT-MRAM based counterparts.

References

[1]

Rastegari, M., Ordonez, V., Redmon, J., & Farhadi, A. (2016, October). Xnor-net: Imagenet classification using binary convolutional neural networks. In European Conference on Computer Vision (pp. 525--542). Springer, Cham.

Crossref

Google Scholar

[2]

Khwa, W. S., Chen, J. J., Li, J. F., Si, X., Yang, E. Y., Sun, X., ... & Chang, M. F. (2018, February). A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors. In Solid-State Circuits Conference-(ISSCC), 2018 IEEE International (pp. 496--498). IEEE.

Google Scholar

[3]

Choi, Y. G., Yoo, S., Lee, S., & Ahn, J. H. (2011, June). Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache. In Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE (pp. 978--983). IEEE.

Digital Library

Google Scholar

[4]

Tang, T., Xia, L., Li, B., Wang, Y., & Yang, H. (2017, January). Binary convolutional neural network on rram. In Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific (pp. 782--787). IEEE.

Google Scholar

[5]

Angizi, S., He, Z., Parveen, F., & Fan, D. (2018, January). IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (pp. 111--116). IEEE Press.

Digital Library

Google Scholar

[6]

Sun, Z., Wu, W., & Li, H. (2013, May). Cross-layer racetrack memory design for ultra high density and low power consumption. In Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE (pp. 1--6). IEEE.

Digital Library

Google Scholar

[7]

Fert, A., Cros, V., & Sampaio, J. (2013). Skyrmions on the track. Nature nanotechnology, 8(3), 152.

Google Scholar

[8]

Kang, W., Huang, Y., Zheng, C., Lv, W., Lei, N., Zhang, Y., ... & Zhao, W. (2016). Voltage controlled magnetic skyrmion motion for racetrack memory. Scientific reports, 6, 23164.

Google Scholar

[9]

Huang, Y., Kang, W., Zhang, X., Zhou, Y., & Zhao, W. (2017). Magnetic skyrmion-based synaptic devices. Nanotechnology, 28(8), 08LT02.

Google Scholar

[10]

Li, S., Kang, W., Huang, Y., Zhang, X., Zhou, Y., & Zhao, W. (2017). Magnetic skyrmion-based artificial neuron device. Nanotechnology, 28(31), 31LT01.

Google Scholar

[11]

Zhao, W., Chappert, C., Javerliac, V., & Noziere, J. P. (2009). High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits. IEEE Transactions on Magnetics, 45(10), 3784--3787.

Crossref

Google Scholar

Cited By

View all

Chang JChen T(2022)When B-Tree Meets Skyrmion Memory: How Skyrmion Memory Affects an Indexing SchemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319751941:11(3814-3825)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1109/TCAD.2022.3197519
Wang JLiu JWang DAn JFan X(2022)An Automatic-Addressing Architecture With Fully Serialized Access in Racetrack Memory for Energy-Efficient CNNsIEEE Transactions on Computers10.1109/TC.2020.304543371:1(235-250)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TC.2020.3045433
Gnoli LRiente FVacca MRuo Roch MGraziano M(2021)Skyrmion Logic-In-Memory Architecture for Maximum/Minimum SearchElectronics10.3390/electronics1002015510:2(155)Online publication date: 12-Jan-2021
https://doi.org/10.3390/electronics10020155
Show More Cited By

Index Terms

A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network
1. Hardware

Recommendations

Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache Devices
ISLPED '22: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

Skyrmion racetrack memory (SK-RM) has been regarded as a promising alternative to replace static random-access memory (SRAM) as a large-size on-chip cache device with high memory density. Different from other nonvolatile random-access memories (NVRAMs),...
A durable and energy efficient main memory using phase change memory technology
ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture

Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile ...
A durable and energy efficient main memory using phase change memory technology

Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile ...

Comments

Information & Contributors

Information

Published In

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

May 2019

562 pages

ISBN:9781450362528

DOI:10.1145/3299874

General Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA
,
Program Chairs:
Tinoosh Mohsenin
UMBC, USA
,
Weisheng Zhao
Beihang University, China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 May 2019

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Beihang University Hefei Innovation Research Institute
Special Foundation of Beijing Municipal Science & Technology Commission
National Science Foundation for Young Scientists of China

Conference

GLSVLSI '19

Sponsor:

SIGDA

GLSVLSI '19: Great Lakes Symposium on VLSI 2019

May 9 - 11, 2019

VA, Tysons Corner, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Upcoming Conference

GLSVLSI '25

Sponsor:
sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
281
Total Downloads

Downloads (Last 12 months)14
Downloads (Last 6 weeks)2

Reflects downloads up to 25 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Chang JChen T(2022)When B-Tree Meets Skyrmion Memory: How Skyrmion Memory Affects an Indexing SchemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319751941:11(3814-3825)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1109/TCAD.2022.3197519
Wang JLiu JWang DAn JFan X(2022)An Automatic-Addressing Architecture With Fully Serialized Access in Racetrack Memory for Energy-Efficient CNNsIEEE Transactions on Computers10.1109/TC.2020.304543371:1(235-250)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TC.2020.3045433
Gnoli LRiente FVacca MRuo Roch MGraziano M(2021)Skyrmion Logic-In-Memory Architecture for Maximum/Minimum SearchElectronics10.3390/electronics1002015510:2(155)Online publication date: 12-Jan-2021
https://doi.org/10.3390/electronics10020155
Xu RSha EZhuge QShi LGu S(2020)Architectural Exploration on Racetrack Memories2020 IEEE 33rd International System-on-Chip Conference (SOCC)10.1109/SOCC49529.2020.9524792(31-36)Online publication date: 8-Sep-2020
https://doi.org/10.1109/SOCC49529.2020.9524792

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache Devices

A durable and energy efficient main memory using phase change memory technology

A durable and energy efficient main memory using phase change memory technology

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Funding Sources

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations