research-article

Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing

Authors:

Adarsha Balaji,

Francky Catthoor,

Siebren SchaafsmaAuthors Info & Claims

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

Pages 495 - 499

https://doi.org/10.1145/3299874.3319491

Published: 13 May 2019 Publication History

Abstract

Spiking Neural Networks (SNNs) are efficient computation models for spatio-temporal pattern recognition on resource and power constrained platforms. Dedicated SNN hardware, also called neuromorphic hardware, can further reduce the energy consumption of these platforms. A neuromorphic hardware consists of crossbars, which are arrangements of input and output neurons with fully-connected synapses. Time-multiplexed interconnects are used to communicate spikes between crossbars. When a SNN model is mapped on multiple crossbars, the time-multiplexed interconnect increases spike latency and energy consumption, and disorders spike arrivals at output neurons, which reduces application accuracy. In this paper, we propose segmented bus interconnect for global synapses in a neuromorphic architecture. The objective is to reduce power consumption and enable parallel processing compared to traditional time-multiplexed interconnects. The fundamental idea for the segmented bus is to partition a single bus into several segments, with the segmentation switches controlled by software. We evaluate the scalability of segmented bus using synthetic applications. Our results show that segmented bus reduces the latency and energy consumption of the global synapse network significantly with respect to state-of-the-art techniques.

References

[1]

Filipp Akopyan et al. 2015. TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip. IEEE TCAD (2015).

[2]

Luca Benini and Giovanni De Micheli. 2002. Networks on chip: A new paradigm for systems on chip design. In DATE.

[3]

Kwabena A. Boahen. 1998. Communicating neuronal ensembles between neuromorphic chips. In Neuromorphic systems engineering.

Digital Library

[4]

Vincenzo Catania et al. 2015. Noxim: An open, extensible and cycle-accurate network on chip simulator. In ASAP.

[5]

J. Chen et al. 1999. Segmented bus design for low-power systems. IEEE TVLSI (1999).

Digital Library

[6]

T. Chou et al. 2018. CARLsim 4: An Open Source Library for Large Scale, Biologically Detailed Spiking Neural Network Simulation using Heterogeneous Clusters. In IJCNN.

[7]

A. Das et al. 2018. Mapping of local and global synapses on spiking neuromorphic hardware. In DATE.

[8]

Anup Das and Akash Kumar. 2018. Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware. In GLSVLSI.

Digital Library

[9]

P. Diehl et al. 2015. Unsupervised learning of digit recognition using spike-timing-dependent plasticity. Frontiers in computational neuroscience (2015).

[10]

Francesco Galluppi et al. 2012. A hierachical configuration system for a massively parallel neural hardware platform. In CF.

Digital Library

[11]

Yatin Hoskote et al. 2007. A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro (2007).

Digital Library

[12]

Giacomo Indiveri et al. 2015. Neuromorphic architectures for spiking deep neural networks. In IEDM.

[13]

Yu Ji et al. 2016. NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. In MICRO.

Digital Library

[14]

Muhammad Mukaram Khan et al. 2008. SpiNNaker: mapping neural networks onto a massively-parallel chip multiprocessor. In IJCNN.

[15]

Hee-choul Lee. 2002. Multi-stage interconnection network for high speed packet switching. US Patent 6,335,930.

[16]

Xiaoxiao Liu et al. 2018. Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems. In ASP-DAC.

Digital Library

[17]

Wolfgang Maass. 1997. Networks of spiking neurons: the third generation of neural network models. Neural networks, Vol. 10, 9 (1997), 1659--1671.

Digital Library

[18]

Wei Zhao and Yu Cao. 2006. New generation of predictive technology model for sub-45 nm early design exploration. IEEE TED (2006).

Cited By

Mayahinia MMarinelli TPei ZLiu HPan CTokei ZCatthoor FTahoori M(2024)Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant NodesIEEE Embedded Systems Letters10.1109/LES.2024.344471116:4(321-324)Online publication date: Dec-2024
https://doi.org/10.1109/LES.2024.3444711
Sahoo SDas AKumar A(2024)Fault Tolerant ArchitecturesHandbook of Computer Architecture10.1007/978-981-97-9314-3_11(277-320)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_11
Tang GVadivel KXu YBilgic RShidqi KDetterer PTraferro SKonijnenburg MSifalakis Mvan Schaik GYousefzadeh A(2023)SENECA: building a fully digital neuromorphic processor, design trade-offs and challengesFrontiers in Neuroscience10.3389/fnins.2023.118725217Online publication date: 23-Jun-2023
https://doi.org/10.3389/fnins.2023.1187252
Show More Cited By

Index Terms

Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing
1. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
      1. Emerging architectures
    2. Biology-related information processing
      1. Neural systems
  2. Integrated circuits
    1. Interconnect

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cover image ACM Conferences

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

May 2019

562 pages

ISBN:9781450362528

DOI:10.1145/3299874

General Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA
,
Program Chairs:
Tinoosh Mohsenin
UMBC, USA
,
Weisheng Zhao
Beihang University, China

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 May 2019

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EU-H2020
ITEA3

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GLSVLSI '19

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SIGDA

GLSVLSI '19: Great Lakes Symposium on VLSI 2019

May 9 - 11, 2019

VA, Tysons Corner, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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June 30 - July 2, 2025

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Cited By

Mayahinia MMarinelli TPei ZLiu HPan CTokei ZCatthoor FTahoori M(2024)Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant NodesIEEE Embedded Systems Letters10.1109/LES.2024.344471116:4(321-324)Online publication date: Dec-2024
https://doi.org/10.1109/LES.2024.3444711
Sahoo SDas AKumar A(2024)Fault Tolerant ArchitecturesHandbook of Computer Architecture10.1007/978-981-97-9314-3_11(277-320)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_11
Tang GVadivel KXu YBilgic RShidqi KDetterer PTraferro SKonijnenburg MSifalakis Mvan Schaik GYousefzadeh A(2023)SENECA: building a fully digital neuromorphic processor, design trade-offs and challengesFrontiers in Neuroscience10.3389/fnins.2023.118725217Online publication date: 23-Jun-2023
https://doi.org/10.3389/fnins.2023.1187252
Varshika MMishra AKandasamy NDas ATakahashi A(2023)Hardware-Software Co-Design for On-Chip Learning in AI SystemsProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3568359(624-631)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3568359
Balaji AHuynh PCatthoor FDutt NKrichmar JDas A(2023)NeuSB: A Scalable Interconnect Architecture for Spiking Neuromorphic HardwareIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2023.323870811:2(373-387)Online publication date: 1-Apr-2023
https://doi.org/10.1109/TETC.2023.3238708
Sahoo SDas AKumar A(2023)Fault Tolerant ArchitecturesHandbook of Computer Architecture10.1007/978-981-15-6401-7_11-1(1-44)Online publication date: 17-Feb-2023
https://doi.org/10.1007/978-981-15-6401-7_11-1
Varshika MDas A(2023)Platform-Based Design of Embedded Neuromorphic SystemsEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-19568-6_12(337-358)Online publication date: 1-Oct-2023
https://doi.org/10.1007/978-3-031-19568-6_12
Paul ATajin MDas AMongan WDandekar K(2022)Energy-Efficient Respiratory Anomaly Detection in Premature Newborn InfantsElectronics10.3390/electronics1105068211:5(682)Online publication date: 23-Feb-2022
https://doi.org/10.3390/electronics11050682
Varshika MBalaji ACorradi FDas AStuijt JCatthoor F(2022)Design of Many-Core Big Little µBrains for Energy-Efficient Embedded Neuromorphic Computing2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774613(1011-1016)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774613
Song SBalaji ADas AKandasamy N(2022)Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing ElementsACM Transactions on Embedded Computing Systems10.1145/352406821:6(1-27)Online publication date: 12-Dec-2022
https://dl.acm.org/doi/10.1145/3524068
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