research-article

Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing

Authors:

Iris Hui-Ru Jiang,

Gi-Joon NamAuthors Info & Claims

ISPD '19: Proceedings of the 2019 International Symposium on Physical Design

Pages 11 - 18

https://doi.org/10.1145/3299902.3309753

Published: 04 April 2019 Publication History

Abstract

As the wide adoption of FinFET technology in mass production, dynamic power becomes the bottleneck to achieving low power. Therefore, clock power reduction is crucial in modern IC design. Register clustering can effectively save clock power because of significantly reducing the number of clock sinks and register pin capacitance, clock routed wirelength, and the number of clock buffers. In this paper, we propose effective mean shift to naturally form clusters according to register distribution without placement disruption. Effective mean shift fulfills the requirements to be a good register clustering algorithm because it needs no prespecified number of clusters, is insensitive to initializations, is robust to outliers, is tolerant of various register distributions, is efficient and scalable, and balances clock power reduction against timing degradation. Experimental results show that our approach outperforms state-of-the-art work on power and timing balancing, as well as efficiency and scalability.

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Cited By

Kim SKim T(2025)Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.345783444:3(1084-1097)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3457834
Hsieh YLin TChang YWu HJiang I(2025)Graceful Register Clustering and Rebanking for Power and Timing BalancingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344823344:3(1070-1083)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3448233
Kahng AWang Z(2025)DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343652144:2(696-708)Online publication date: Feb-2025
https://doi.org/10.1109/TCAD.2024.3436521
Show More Cited By

Index Terms

Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Physical synthesis

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cover image ACM Conferences

ISPD '19: Proceedings of the 2019 International Symposium on Physical Design

April 2019

164 pages

ISBN:9781450362535

DOI:10.1145/3299902

General Chair:
Ismail Bustany
Xilinx Inc.
,
Program Chair:
William Swartz
TimberWolf Systems Inc. & University of Texas at Dallas

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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New York, NY, United States

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Published: 04 April 2019

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ISPD '19: International Symposium on Physical Design

April 14 - 17, 2019

CA, San Francisco, USA

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ISPD '19 Paper Acceptance Rate 12 of 25 submissions, 48%;

Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25

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March 16 - 19, 2025

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Cited By

Kim SKim T(2025)Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.345783444:3(1084-1097)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3457834
Hsieh YLin TChang YWu HJiang I(2025)Graceful Register Clustering and Rebanking for Power and Timing BalancingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344823344:3(1070-1083)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3448233
Kahng AWang Z(2025)DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343652144:2(696-708)Online publication date: Feb-2025
https://doi.org/10.1109/TCAD.2024.3436521
Roman-Vicharra CChen YHu JAmrouch HHu JGarg SLin Y(2024)Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power OptimizationProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685949(1-7)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685949
Chen YWu HJiang ITsai CWu CHui-Ru Jiang IPosser G(2024)Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-FlopsProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3633327(21-29)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3633327
Roman-Vicharra CChen YHu J(2024)Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD)10.1109/MLCAD62225.2024.10740200(1-7)Online publication date: 9-Sep-2024
https://doi.org/10.1109/MLCAD62225.2024.10740200
Liu MLai YMak WWang TMitra TYoung EXiong J(2022)Generation of Mixed-Driving Multi-Bit Flip-Flops for Power OptimizationProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549473(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549473
Huang CTeller GNam GChang YLi Z(2020)Latch clustering for timing-power co-optimizationProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437769(1-6)Online publication date: 20-Jul-2020
https://dl.acm.org/doi/10.5555/3437539.3437769
Huang CTellez GNam GChang Y(2020)Latch Clustering for Timing-Power Co-Optimization2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218617(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218617

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