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The Design and Implementation of a Latency-Aware Packet Classification for OpenFlow Protocol based on FPGA

Published: 14 December 2018 Publication History

Abstract

Packet classification has been recognized as one of the most significant functions in contemporary network infrastructures. Furthermore, a number of modern applications such as IoTs contain very strict constraints on the latency of network transmissions. This paper presents the design and implementation of a novel packet classification based on FPGA architecture. The proposed design contains a Latency Compression Scheme (LCS) to achieve the low-latency packet processing. Furthermore, this structure supports 12-tuple fields for the modern Internet traffics. The experimental results show that the proposed packet classification scheme reduces the delay of packet processing by 2.18× compared to the state-of-the-art works.

References

[1]
Software-Defined Networking (SDN) Definition. {Online}. Available: https://www.opennetworking.org/den-resources/sdn-definition/.
[2]
M. Ojo et al., "A SDN-IoT Architecture with NFV Implementation," in 2016 IEEE Globecom Workshops, 2016 © IEEE.
[3]
Y.-W. Ma et al., "SDN-enabled network virtualization for industry 4.0 based on IoTs and cloud computing," in 19th Int. Conf. Advanced Communication Technology, Bongpyeong, South Korea, 2017, pp. 199--202.
[4]
OpenFlow Switch Specification V1.0.0. {Online}. Available: https://www.opennetworking.org/wp-content/uploads/2013/04/openflow-spec-v1.0.0.pdf, 2009.
[5]
J. M. Llopis et al., "Minimizing Latency of Critical Traffic through SDN," in 2016 IEEE Int. Conf. Networking, Architecture and Storage, 2016 © IEEE.
[6]
P. Schulz et al., "Latency Critical IoT Applications in 5G: Perspective on the Design of Radio Interface and Network Architecture," IEEE Commun. Magazine, Vol. 55, no. 2, pp. 70--78, Feb., 2017.
[7]
F. Yu et al., "Efficient Multimatch Packet Classification and Lookup with TCAM," IEEE Micro, vol. 25, no. 1, pp. 50--59, 2005.
[8]
K. Lakshminarayanan et al., "Algorithms for Advanced Packet Classification with Ternary CAMs," in Proc. ACM SIGCOMM, 2005, pp. 193--204.
[9]
Y.-K. Chang and C.-S. Hsueh, "Range-Enhanced Packet Classification," IEEE Trans. Emerging Topics in Computing, vol. 4, no. 2, pp. 214--224, Jun. 2016.
[10]
Y. R. Qu and V. K. Prasanna, "High-Performance and Dynamically Updatable Packet Classification Engine on FPGA", IEEE Trans. Parallel Distrib. Syst., vol. 27, no. 1, pp.197--209, Jan. 2016.
[11]
Xilinx, Inc., San Jose, CA, "Virtex-6 Family Overview," 2015. {Online}. Available: https://www.xilinx.com/support/documentation/data_sheets/ds150.pdf
[12]
W. Jiang and V. K. Prasanna, "Field-split Parallel Architecture for High Performance Multi-match Packet Classification using FPGAs," in Proc. 21st Annu. Symp. Parallelism in Algorithms and Architectures, 2009, pp. 188--196.
[13]
V. Srinivasan et al., "Fast and Scalable Layer Four Switching," in Proc. ACM SIGCOMM, 1998, pp. 191--202.
[14]
E. Spitznagel et al., "Packet classification using extended TCAMs," in Proc. IEEE Int. Conf. Network Protocols, 2003, pp. 120--131.
[15]
T. Ganegedara and V. K. Prasanna, "StrideBV: Single chip 400G+ packet classification," in Proc. IEEE 13th Int. Conf. High Performance Switching and Routing, 2012, pp. 1--6.
[16]
P. Gupta and N. McKeown, "Algorithms for packet classification," IEEE Netw., vol. 15, no. 2, pp. 24--32, Mar. 2001.

Cited By

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  • (2022)PextCuts: A High-performance Packet Classification Algorithm with Pext CPU Instruction2022 IEEE/ACM 30th International Symposium on Quality of Service (IWQoS)10.1109/IWQoS54832.2022.9812873(1-10)Online publication date: 10-Jun-2022
  • (2021)MultilayerTuple: A General, Scalable and High-performance Packet Classification Algorithm for Software Defined Network System2021 IFIP Networking Conference (IFIP Networking)10.23919/IFIPNetworking52078.2021.9472824(1-9)Online publication date: 21-Jun-2021

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  1. The Design and Implementation of a Latency-Aware Packet Classification for OpenFlow Protocol based on FPGA

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    cover image ACM Other conferences
    ICNCC '18: Proceedings of the 2018 VII International Conference on Network, Communication and Computing
    December 2018
    372 pages
    ISBN:9781450365536
    DOI:10.1145/3301326
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 14 December 2018

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    Author Tags

    1. FPGA
    2. Latency-Aware
    3. OpenFlow
    4. Packet classification

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    • (2022)PextCuts: A High-performance Packet Classification Algorithm with Pext CPU Instruction2022 IEEE/ACM 30th International Symposium on Quality of Service (IWQoS)10.1109/IWQoS54832.2022.9812873(1-10)Online publication date: 10-Jun-2022
    • (2021)MultilayerTuple: A General, Scalable and High-performance Packet Classification Algorithm for Software Defined Network System2021 IFIP Networking Conference (IFIP Networking)10.23919/IFIPNetworking52078.2021.9472824(1-9)Online publication date: 21-Jun-2021

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