GLSVLSI

We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate ...

The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected local and global clock rates for high performance processors. Physical short-...

Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Various coding schemes have been proposed in literature to encode the input signal in order to reduce the number of transitions. Number of transitions can ...

System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional blocks. We focus on power estimation for data-dominated systems specified ...

In order to overcome the limitations of automated tools and the cumbersome proof process of interactive theorem proving, we adopt a hybrid approach for formal hardware verification which uses the strengths of theorem proving (HOL) with powerful ...

This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS + micromachining) SOC device, or alternatively as a hybrid ...

Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable ...

Symbolic Model checking is a widely used technique in sequential verification. As the size of the OBDDs and also the computation time depends on the order of the input variables, the verification may only succeed if a well suited variable order is ...

Formal verification of integer multipliers was an open problem for a long time as the size of any reduced ordered binary decision diagram (BDD) [1] which represents integer multiplication is exponential in the width of the operands [2]. In 1995, Bryant ...

Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the interconnect problem by reducing wire lengths directly. We present a non-...

In this paper, we present high-performance bidirectional repeaters that recondition the signal waveform and reduce the signal degradation. We also present the application of these repeaters to the design of high-performance bidirectional busses. SPICE ...

We propose an accurate measure of channel routing density and its application to global routing. Our congestion metric calculation method considers the wire scenarios in a channel.

The concept of a “transparent repeater¹,” which is an amplifier circuit designed to minimize the delay introduced by highly resistive interconnect lines in high speed digital circuits, is introduced and described in this paper. An insertion methodology ...

In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time and power. The design approach considered in this paper allows the ...

We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuously analyzing the congestion at all steps, nets are incrementally globally ...

With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. We present an accurate technique for modeling and analyzing the effects of ...

We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the population. This uses considerably less memory compared to a method with ...

Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive ...

In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of different performance measures of the chip, namely area, delay and power ...

In this paper the results of an experimental comparison of popular pass-transistor logic families in 1.5V, 0.18µm CMOS technology using advanced CAD tools for circuit tuning and simulation are presented. The logic families were compared using an ...

Numerous efforts in balancing the trade-off between power, area and performance have been carried out in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design ...

A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. The low power dissipation is a vital factor when we consider the ...

This paper investigates the effectiveness of combination of different low power SRAM circuit design techniques. The divided bit line (DBL), pulsed word line (PWL) and isolated bit line (IBL) strategies have been implemented in a various size SRAM ...

The trend in computer performance over the last 20 years has indicated that the memory performance constitutes a bottlneck for the overall system performance. As a result, smaller, faster memories have been introduced to hide the speed differential ...

In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application of interest. Our proposed technique can be used to compute a tighter ...

This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously, a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the ...

In this paper, we present an efficient approach to find effective module selections under resource, latency, and power constraints. The framework contains two phases: choosing a resource configuration, and determining a module binding for each resource. ...