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A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors

Published: 11 March 2019 Publication History

Abstract

Smart systems are characterized by the integration in a single device of multi-domain subsystems of different technological domains, namely, analog, digital, discrete and power devices, MEMS, and power sources. Such challenges, emerging from the heterogeneous nature of the whole system, combined with the traditional challenges of digital design, directly impact on performance and on propagation delay of digital components.
This article proposes a design approach to enhance the RTL model of a given digital component for the integration in smart systems with the automatic insertion of delay sensors, which can detect and correct timing failures. The article then proposes a methodology to verify such added features at system level. The augmented model is abstracted to SystemC TLM, which is automatically injected with mutants (i.e., code mutations) to emulate delays and timing failures. The resulting TLM model is finally simulated to identify timing failures and to verify the correctness of the inserted delay monitors. Experimental results demonstrate the applicability of the proposed design and verification methodology, thanks to an efficient sensor-aware abstraction methodology, by applying the flow to three complex case studies.

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  • (2020)ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116573(1508-1513)Online publication date: Mar-2020

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        cover image ACM Transactions on Design Automation of Electronic Systems
        ACM Transactions on Design Automation of Electronic Systems  Volume 24, Issue 3
        May 2019
        266 pages
        ISSN:1084-4309
        EISSN:1557-7309
        DOI:10.1145/3319359
        • Editor:
        • Naehyuck Chang
        Issue’s Table of Contents
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Publication History

        Published: 11 March 2019
        Accepted: 01 January 2019
        Revised: 01 October 2018
        Received: 01 June 2018
        Published in TODAES Volume 24, Issue 3

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        Author Tags

        1. Timing monitors
        2. code abstraction
        3. razor sensor
        4. systemc TLM
        5. verification

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        • (2020)ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116573(1508-1513)Online publication date: Mar-2020

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